CY25200
Programmable Spread Spectrum
Clock Generator for EMI Reduction
Programmable Spread Spectrum Clock Generator for EMI Reduction
Features
Description
■ Wide Operating Output (SSCLK) Frequency Range
❐ 3 to 200 MHz
The CY25200 is a programmable clock generator with spread
spectrum capability. Spread spectrum modulates the output
clock frequency over a small range, spreading the energy and
reducing the energy peak. This is a powerful technique to reduce
EMI in a variety of applications.
■ Programmable Spread Spectrum with Nominal 31.5 kHz
modulation Frequency
■ Center Spread: ±0.25% to ±2.5%
■ Down Spread: –0.5% to –5.0%
It uses either an external reference clock or a crystal for an input.
It also uses a PLL to generate a spread spectrum output clock
that can be a different frequency than the input. Up to six output
clocks are available and up to two of them can be REFCLKs
(copies of the input clock, without spread).
■ Input Frequency Range
❐ External crystal: 8 to 30 MHz fundamental crystals
❐ External reference: 8 to 166 MHz clock
The CY25200 is highly configurable. Programmable variables
include the input and output frequencies, spread percentage,
center spread or down spread, and control pin functions. The
oscillator pin capacitance can also be programmed to match the
load capacitance requirement (CL)of the crystal, eliminating the
need for external capacitors.
■ Integrated Phase-Locked Loop (PLL)
■ Programmable Crystal Load Capacitor Tuning Array
■ Low Cycle-to-Cycle Jitter
■ 3.3 V Operation with 2.5 V Output Clock Drive Option
■ Spread Spectrum On and Off Function
■ Power Down or Output Enable Function
■ Output Frequency Select Option
Available features include Output Enable, Power Down, Spread
On/Off, Frequency Select, and the option to power some output
clocks at 2.5 V.
Cypress’ web-based CyberClocks Online software is used to
configure the device. Programmability enables fast prototyping,
which is particularly useful when doing EMC testing and
determining the optimal spread settings.
■ Field-Programmable
■ Package: 16 Pin TSSOP
Logic Block Diagram
SSCLK1
SSCLK2
7
Divider
Bank 1
8
Output
Select
Matrix
9
SSCLK3
SSCLK4
XIN/CLKIN
XOUT
1
Q
OSC.
12
VCO
16
P
C
XOUT
C
Divider
Bank 2
XIN
PLL
14
15
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
6
2
3
5
11
4
10
13
AVSS VSS
VDD
AVDD
VDDL VSSL
CP0 CP1
Cypress Semiconductor Corporation
Document Number: 38-07633 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 7, 2010
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