Datasheet > PPXD4030VVU264R

PPXD4030VVU264R

更新时间： 2022-03-18 07:39:19

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
23页	116K
描述
32-bit Power ArchitectureÂ® Microcontrollers for Real-Time Applications

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中文翻译

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数据手册

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PPXD4030VVU264R 数据手册

Features

— Minimizes impact on performance

•

Six read and three write operations per clock

— Integrates a pair of integer execution units, a branch control unit, instruction fetch unit and

load/store unit, and a multi-ported register file

•

Branch target prefetching performed by the branch unit allows single-cycle branches in many cases

16 KB instruction cache and 16 KB data cache, both supporting error detection hardware.

Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer (TLB)

Nexus Class 3+ module

Supports non-maskable interrupt (completely un-maskable and not guaranteed to be recoverable)

and critical interrupt (an interrupt that can be masked and is guaranteed to be recoverable) sources

— Routed from a single package pin, via edge detection logic in the SIU, to the CPU

An additional Wait for Interrupt instruction:

•

— Used in conjunction with low power STOP mode

— Instruction stops the system clock

— An external interrupt source or the system wake-up timer restart the system clock, allowing the

CPU to service the interrupt

•

Includes multiple input signature register (MISR) hardware which can be accessed by software to

implement CPU self test functionality

2.5.2

On-chip flash memory

The PXR40 flash memory module provides the following:

•

4 MB of programmable, non-volatile, flash memory

— Nonvolatile memory (NVM) can be used for instruction and/or data storage

•

A fetch accelerator optimizes the performance of the flash memory array to match the CPU

architecture

— Architected to optimize the performance of the flash memory with the CPU to provide

single-cycle random access to the flash memory when in full clock mode, and two-cycle access

when in double clock mode

— Configurable read buffering and line prefetch support

•

An interface between the system bus and a dedicated flash memory array controller

Supports a 64-bit data bus width at the system bus port for CPU loads, DMA transfers and CPU

instruction fetch

— Byte, halfword, word, and doubleword reads are supported

— Only aligned word and doubleword writes are supported

•

Hardware and software configurable read and write access protections on a per-master basis

Pipelined interface to the flash memory array controller allowing overlapped accesses to proceed

in parallel for interleaved or pipelined flash memory array designs

•

Configurable access timing allowing use in a wide range of system frequencies

PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1...3 4 567 8 9...23

中文翻译

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与PPXD4030VVU264R相关器件

型号	品牌	获取价格	描述	数据表
PPXI-V04-FX-1152-01	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-02	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-03	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-04	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-05	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-08	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-09	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1152-10	SAMTEC	获取价格	IC Socket, FPGA1152, 1152 Contact(s),
PPXI-V04-FX-1517-03	SAMTEC	获取价格	IC Socket, FPGA1517, 1517 Contact(s),
PPXI-V04-FX-1517-06	SAMTEC	获取价格	IC Socket, FPGA1517, 1517 Contact(s),

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