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PPG36F-2MC5

更新时间： 2024-11-24 09:47:35
品牌 Logo 应用领域
DATADELAY 逻辑集成电路延迟线
页数 文件大小 规格书
5页 47K
描述
Pulse Generator Delay Line, Programmable, 1-Func, 63-Tap, Complementary Output,

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PPG36F-2MC5 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active包装说明：SOP,
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.81JESD-30 代码：R-XDSO-G24
长度：32.512 mm逻辑集成电路类型：PULSE GENERATOR DELAY LINE
功能数量：1抽头/阶步数：63
端子数量：24输出极性：COMPLEMENTARY
封装主体材料：UNSPECIFIED封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED可编程延迟线：YES
认证状态：Not Qualified座面最大高度：7.112 mm
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
端子形式：GULL WING端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总延迟标称（td）：126 nsBase Number Matches：1

PPG36F-2MC5 数据手册

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PPG36F  
Ò
6-BIT PROGRAMMABLE  
PULSE GENERATOR  
(SERIES PPG36F)  
data  
delay  
devices,  
3
inc.  
FEATURES  
PACKAGES  
TRIG  
N/C  
OUT  
N/C  
N/C  
N/C  
RES  
N/C  
N/C  
N/C  
N/C  
GND  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
OUT/  
N/C  
N/C  
N/C  
A0  
·
·
·
·
·
·
·
·
·
Digitally programmable in 64 steps  
Monotonic pulse-width-vs-address variation  
Rising edge triggered  
Two separate outputs: inverting & non-inverting  
Precise and stable pulse width  
Input & outputs fully TTL interfaced & buffered  
10 T2L fan-out capability  
2
3
4
5
6
A1  
7
A2  
8
9
N/C  
A3  
Fits standard 24-pin DIP socket  
Auto-insertable  
10  
11  
12  
A4  
A5  
PPG36F-xx  
DIP  
PPG36F-xxM  
Military DIP  
PPG36F-xxC4 Gull-Wing  
PPG36F-xxMC4 Military Gull-Wing  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The PPG36F-series device is a 6-bit digitally programmable pulse  
generator. The width, PWA, depends on the address code (A5-A0)  
according to the following formula:  
TRIG Trigger Input  
OUT Non-inverted Output  
OUT/ Inverted Output  
A0-A5 Address Bits  
RES Reset  
PWA = PW0 + TINC * A  
VCC +5 Volts  
GND Ground  
where A is the address code, TINC is the incremental pulse width of the  
device, and PW0 is the inherent pulse width of the device. The incremental  
width is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively.  
RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into  
LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not  
latched and must remain asserted while the output pulse is active.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
·
Programmed pulse width tolerance: 5% or 2ns,  
whichever is greater  
Part  
Number  
Incremental Width  
Per Step (ns)  
0.5 ± 0.3  
1 ± 0.5  
Total Width  
Change (ns)  
31.5 ± 2.00  
63.0 ± 3.15  
126.0 ± 6.30  
189.0 ± 9.45  
252.0 ± 12.6  
315.0 ± 15.8  
378.0 ± 18.9  
441.0 ± 22.1  
504.0 ± 25.2  
567.0 ± 28.4  
630.0 ± 31.5  
PPG36F-.5  
PPG36F-1  
PPG36F-2  
PPG36F-3  
PPG36F-4  
PPG36F-5  
PPG36F-6  
PPG36F-7  
PPG36F-8  
PPG36F-9  
PPG36F-10  
·
·
·
·
·
Inherent width (PW0): 12ns typical  
Inherent delay (TTO): 3.5ns ± 2ns  
Operating temperature: 0° to 70° C  
Supply voltage VCC: 5VDC ± 5%  
Supply current: ICC = 60ma typical  
2 ± 0.5  
3 ± 1.0  
4 ± 1.0  
5 ± 1.5  
6 ± 1.5  
7 ± 1.5  
8 ± 2.0  
9 ± 2.0  
10 ± 2.0  
NOTE: Any dash number between .5 and 10 not  
shown is also available.  
Ó1997 Data Delay Devices  
Doc #97009  
1/15/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
12345

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