Datasheet > PPC5567MVR132R2

PPC5567MVR132R2

更新时间： 2024-12-01 06:04:47

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
56页	1255K
描述
Microcontroller

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数据手册

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PPC5567MVR132R2 数据手册

Document Number: MPC5567

Rev. 0, 06/2006

Freescale Semiconductor

Data Sheet: Product Preview

MPC5567 Microcontroller

Data Sheet

by: Microcontroller Division

Contents

This document provides electrical specifications, pin

assignments, and package diagrams for the MPC5567

microcontroller device. For functional characteristics,

refer to the MPC5567 Microcontroller Reference

Manual.

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5

3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 EMI (Electromagnetic Interference) Characteristics 8

3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . . 9

3.7 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 10

3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 12

3.9 Oscillator & FMPLL Electrical Characteristics . . . . 19

3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 20

3.11 H7Fa Flash Memory Electrical Characteristics . . . 21

3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 45

Overview

The MPC5567 microcontroller (MCU) is a member of

the MPC5500 family of microcontrollers based on the

PowerPC™ Book E architecture. This family of parts

contains many new features coupled with high

performance CMOS technology to provide substantial

reduction of cost per feature and significant performance

improvement over the MPC500 family.

Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 53

The host processor core of this device is compatible with

the PowerPC Book E architecture. It is 100% user mode

compatible (with floating point library) with the classic

PowerPC instruction set. The Book E architecture has

enhancements that improve the PowerPC architecture’s

fit in embedded applications. This core also has

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

additional instructions, including digital signal

processing (DSP) instructions, beyond the classic

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

• Preliminary—Subject to Change Without Notice

12 3 4 5 6 7...56

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