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PPC440EP-3BB667CX PDF预览

PPC440EP-3BB667CX

更新时间: 2024-11-27 09:10:03
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Microprocessor

PPC440EP-3BB667CX 数据手册

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Part Number 440EP  
Revision 1.26 – April 25, 2007  
Data Sheet  
440EP  
Power PC 440EP Embedded Processor  
Features  
®
• Two Ethernet 10/100Mbps half- or full-duplex  
interfaces. Operational modes supported are MII,  
RMII, and SMII with packet reject.  
• PowerPC 440 processor core operating up to  
667MHz with 32KB I-cache and D-cache with  
parity checking.  
• Up to four serial ports (16750 compatible UART).  
• Selectable processor:bus clock ratios of N:1, N:2.  
• Two USB ports. One USB 1.1 Host interface with  
on-chip PHY. One USB 2.0 Device interface, with  
dedicated DMA, configured as a 1.1 on-chip PHY  
or a 2.0 UTMI.  
• Floating Point Unit with single- and double-  
precision and single-cycle throughput.  
• Dual bridged Processor Local Buses (PLBs) with  
64- and 128-bit widths.  
• External peripheral bus (16-bit data) for up to six  
devices with external mastering.  
• Double Data Rate (DDR) Synchronous DRAM  
(SDRAM) interface operating up to 133MHz with  
ECC.  
• Two IIC interfaces (one with boot parameter read  
capability).  
• DMA support for external peripherals, internal  
UART and memory.  
• NAND Flash interface.  
• SPI interface.  
• PCI V2.2 interface (3.3V only). Thirty-two bits at  
up to 66MHz.  
• General Purpose I/O (GPIO) interface.  
• JTAG interface for board level testing.  
• Programmable interrupt controller supports  
interrupts from a variety of sources.  
• Boot from PCI memory, NOR Flash on the  
external peripheral bus, or NAND Flash on the  
NAND Flash interface.  
• Programmable General Purpose Timers (GPT).  
• Available in RoHS compliant lead-free package.  
Description  
Designed specifically to address high-end embedded  
applications, the PowerPC 440EP (PPC440EP)  
provides a high-performance, low- power solution that  
interfaces to a wide range of peripherals and  
Technology: CMOS Cu-11, 0.13μm.  
Package: 35mm, 456-ball standard plastic ball grid  
array (E-PBGA), with and without lead (RoHS  
compliant).  
incorporates on-chip power management features.  
Typical power (measured): Less than 3W at 533MHz,  
2.5W at 400MHz.  
This chip contains a high-performance RISC  
processor, a floating point unit, DDR SDRAM  
controller, PCI bus interface, control for external ROM  
and peripherals, DMA with scatter-gather support,  
Ethernet ports, serial ports, IIC interfaces, SPI  
interface, USB ports, NAND Flash interface, and  
general purpose I/O.  
Supply voltages required: 3.3V, 2.5V, 1.5V.  
AMCC Proprietary  
1

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