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PLS153 PDF预览

PLS153

更新时间: 2024-01-08 05:36:00
品牌 Logo 应用领域
恩智浦 - NXP 可编程逻辑
页数 文件大小 规格书
9页 147K
描述
Programmable logic arrays 18 】 42 】 10

PLS153 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.79Is Samacsys:N
架构:PLA-TYPEJESD-30 代码:R-PDIP-T20
JESD-609代码:e0输入次数:18
输出次数:10产品条款数:42
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V可编程逻辑类型:OT PLD
传播延迟:40 ns认证状态:Not Qualified
子类别:Programmable Logic Devices标称供电电压:5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

PLS153 数据手册

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Philips Semiconductors Programmable Logic Devices  
Product specification  
Programmable logic arrays  
(18 × 42 × 10)  
PLS153/A  
OR ARRAY – (B)  
P
P
S
S
CODE  
A
CODE  
P
STATUS  
1
P
STATUS  
n
n
INACTIVE  
ACTIVE  
SP00282  
NOTES:  
CAUTION: PLS153A TEST  
COLUMNS  
1. This is the initial unprogrammed state of  
all links.  
The PLS153A incorporates two columns not  
shown in the logic block diagram. These  
columns are used for in-house testing of the  
device in the unprogrammed state. These  
columns must be disabled prior to using the  
PLS153A in your application. If you are using  
a Philips Semiconductors-approved  
programmer, the disabling is accomplished  
during the device programming sequence. If  
these columns are not disabled, abnormal  
operation is possible.  
2. Any gate P will be unconditionally inhibited  
n
if both the Trueand Complement of an input  
(either I or B) are left intact.  
VIRGIN STATE  
A factory shipped virgin device contains all  
fusible links intact, such that:  
1. All outputs are at “H” polarity.  
2. All P terms are disabled.  
n
3. All P terms are active on all outputs.  
n
Furthermore, because of these test columns,  
the PLS153A cannot be programmed using  
the programmer algorithm for the PLS153.  
7
October 22, 1993  

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