Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer
(16 × 45 × 12)
PLS159A
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The PLS159A is a 3-State output, registered
logic element combining AND/OR gate arrays
with clocked J-K flip-flops. These J-K
flip-flops are dynamically convertible to
D-type via a “fold-back” inverting buffer and
• High-speed version of PLS159
N Package
• f
= 18MHz
MAX
– 25MHz clock rate
• Field-Programmable (Ni-Cr link)
• 4 dedicated inputs
• 13 control gates
20
19
18
17
16
15
14
13
12
11
CLK
I0
1
2
3
4
5
6
7
8
9
V
CC
F7
F6
F5
F4
F3
F2
F1
F0
OE
control gate F . It features 8 registered I/O
C
I1
outputs (F) in conjunction with 4 bidirectional
I/O lines (B). These yield variable I/O gate
and register configurations via control gates
(D, L) ranging from 16 inputs to 12 outputs.
I2
I3
• 32 AND gates
B0
B1
B2
B3
The AND/OR arrays consist of 32 logic AND
gates, 13 control AND gates, and 21 OR
gates with fusible link connections for
programming I/O polarity and direction. All
AND gates are linked to 4 inputs (I),
bidirectional I/O lines (B), internal flip-flop
outputs (Q), and Complement Array output
(C). The Complement Array consists of a
NOR gate optionally linked to all AND gates
for generating and propagating
• 21 OR gates
• 45 product terms:
– 32 logic terms
– 13 control terms
GND 10
• 4 bidirectional I/O lines
N = Plastic Dual In-Line Package (300mil-wide)
• 8 bidirectional registers
• J-K, T, or D-type flip-flops
complementary AND terms.
• Power-on reset feature on all flip-flops
On-chip T/C buffers couple either True (I, B,
Q) or Complement (I, B, Q, C) input polarities
to all AND gates, whose outputs can be
optionally linked to all OR gates. Any of the
32 AND gates can drive bidirectional I/O lines
(B), whose output polarity is individually
programmable through a set of Ex-OR gates
for implementing AND-OR or AND-NOR logic
functions. Similarly, any of the 32 AND gates
can drive the J-K inputs of all flip-flops. There
are 4 AND gates for the Asynchronous
Preset/Reset functions.
A Package
(F = 1)
n
• Asynchronous Preset/Reset
• Complement Array
CLK
1
I1 I0
F7
V
CC
20 19
3
2
18
17
16
15
14
4
5
6
7
8
F6
F5
F4
F3
F2
I2
I3
• Active-High or -Low outputs
• Programmable OE control
• Positive edge-triggered clock
• Input loading: –100µA (max.)
• Power dissipation: 750mW (typ.)
• TTL compatible
B0
B1
B2
9
10 11 12 13
GND OE
B3
F0 F1
All flip-flops are positive edge-triggered and
can be used as input, output or I/O (for
interfacing with a bidirectional data bus) in
conjunction with load control gates (L),
steering inputs (I), (B), (Q) and
A = Plastic Leaded Chip Carrier
• 3-State outputs
programmable output select lines (E).
APPLICATIONS
• Random sequential logic
The PLS159A is field-programmable,
enabling the user to quickly generate custom
patterns using standard programming
equipment.
• Synchronous up/down counters
• Shift registers
• Bidirectional data buffers
• Timing function generators
• System controllers/synchronizers
• Priority encoder/registers
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
PLS159AN
DRAWING NUMBER
0408D
20-Pin Plastic Dual In-Line Package (300mil-wide)
20-Pin Plastic Leaded Chip Carrier
PLS159AA
0400E
25
October 22, 1993
853–1159 11164