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PL902167USY PDF预览

PL902167USY

更新时间: 2024-09-28 19:44:11
品牌 Logo 应用领域
美国微芯 - MICROCHIP 电信光电二极管电信集成电路
页数 文件大小 规格书
10页 461K
描述
JITTER BLOCKER

PL902167USY 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LSSOP,
Reach Compliance Code:compliantFactory Lead Time:6 weeks
风险等级:5.64JESD-30 代码:R-PDSO-G6
长度:2.9 mm功能数量:1
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1.45 mm标称供电电压:2.5 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.6 mm
Base Number Matches:1

PL902167USY 数据手册

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PL902xxx  
Revision 1.1  
General Description  
Features  
The PL902xxx series is a low-power, small form-factor,  
high-performance OTP-based device and a member of  
Micrel’s JitterBlocker, factory programmable jitter  
attenuators. The JitterBlocker product family cleans any  
deterministic jitter, thereby improving the peak-to-peak  
jitter, accumulated jitter, and even the phase noise. The  
PL902xxx is capable of reducing thousands of  
picoseconds of period jitter in a clock to a level below  
100ps peak-to-peak, making that clock usable for many  
more applications.  
Lowest power and smallest programmable jitter  
attenuator  
Input/output frequency up to 200MHz  
I/O pins can be configured as output enable (OE),  
frequency switching (CSEL), power down (PDB) input,  
or CLK1(2) output.  
<10µA current consumption with PDB active  
Operating temperature range from 40C to +85C  
Available in 6-pin SOT23 GREEN/RoHS-compliant  
packages.  
The PL902xxx operates on a single 2.5V or 3.3V supply,  
consumes little power, and is housed in a small SOT23  
package for a broad range of applications. Programmable  
I/O pins can be configured as output enable (OE),  
configuration select (CSEL), power down (PDB) input, or  
CLK1 (2) output. The power down feature of PL902xxx,  
when activated, allows the IC to consume less than 10µA  
of power, while its programming flexibility allows filtering of  
any clock frequency, up to 200MHz.  
Related devices:  
PL903xxx: Single-ended input, differential output, and  
phase noise cleaning.  
PL904xxx: Differential input, two differential outputs,  
and phase noise cleaning  
Applications  
IEEE1588 GPIO clock cleanup  
FPGA-generated clock cleanup  
1/10/40/100 Gigabit Ethernet (GbE)  
SONET/SDH  
Datasheets and support documentation are available on  
Micrel’s web site at: www.micrel.com.  
Block Diagram  
PCI-Express  
CPRI/OBSAI wireless base stations  
Fibre Channel  
SAS/SATA  
DIMM  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
Revision 1.1  
August 1, 2014  
tcghelp@micrel.com or (408) 955-1690  

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