PL560-69OCR PDF预览

PL560-69OCR

更新时间: 2025-10-14 03:05:39
品牌 Logo 应用领域
PLL 倍频器
页数 文件大小 规格书
15页 887K
描述
Analog Frequency Multiplier

PL560-69OCR 数据手册

 浏览型号PL560-69OCR的Datasheet PDF文件第2页浏览型号PL560-69OCR的Datasheet PDF文件第3页浏览型号PL560-69OCR的Datasheet PDF文件第4页浏览型号PL560-69OCR的Datasheet PDF文件第6页浏览型号PL560-69OCR的Datasheet PDF文件第7页浏览型号PL560-69OCR的Datasheet PDF文件第8页 
Analog Frequency Multiplier  
PL560-xx VCXO Family  
VOLTAGE CONTROL SPECIFICATION  
PARAMETERS  
VCXOꢀStabilizationꢀTimeꢀ  
VCXOꢀTuningꢀRangeꢀ  
SYMBOL  
CONDITIONS  
Fromꢀpowerꢀvalidꢀ  
MIN.  
ꢀꢀ  
TYP.  
MAX.  
UNITS  
msꢀ  
TVCXOSTB  
ꢀ10ꢀ  
XTALꢀC0ꢀ/C1ꢀꢀ<300ꢀ  
200ꢀ  
ppmꢀ  
VCON=ꢀ1.65Vꢀ±ꢀ1.65Vꢀ  
XTALꢀC0ꢀ/C1ꢀꢀ<300ꢀ  
CLKꢀOutputꢀPullabilityꢀ  
±100ꢀ  
±120ꢀ  
ppmꢀ  
Linearityꢀ  
ꢀꢀ  
ꢀ  
ꢀ  
ꢀꢀ  
ꢀꢀ  
5ꢀ  
ꢀꢀ  
10ꢀ  
%ꢀ  
kꢀ  
VCONꢀInputꢀImpedanceꢀ  
VCONꢀModulationꢀBWꢀ  
ꢀꢀ  
130ꢀ  
25ꢀ  
0Vꢀ<ꢀVCONꢀ<ꢀ3.3V,ꢀꢁ3dBꢀ  
ꢀꢀ  
ꢀꢀ  
kHzꢀ  
EXTERNAL COMPONENT VALUES  
INDUCTOR VALUE OPTIMIZATION  
Theꢀrequiredꢀinductorꢀvalue(s)ꢀforꢀtheꢀbestꢀperformanceꢀdependsꢀonꢀtheꢀoperatingꢀfrequency,ꢀandꢀtheꢀboardꢀ  
layoutꢀspecifications.ꢀꢀTheꢀlistedꢀvaluesꢀinꢀthisꢀdatasheetꢀareꢀbasedꢀonꢀtheꢀcalculatedꢀparasiticꢀvaluesꢀfromꢀ  
PhaseLink’sꢀevaluationꢀboardꢀdesign.ꢀꢀTheseꢀinductorꢀvaluesꢀprovideꢀtheꢀuserꢀwithꢀaꢀstartingꢀpointꢀtoꢀdetermineꢀ  
theꢀoptimumꢀinductorꢀvalues.ꢀꢀAdditionalꢀfineꢁtuningꢀmayꢀbeꢀrequiredꢀtoꢀdetermineꢀtheꢀoptimalꢀsolution.ꢀꢀꢀ  
Toꢀassistꢀwithꢀtheꢀinductorꢀvalueꢀoptimization,ꢀPhaseLinkꢀhasꢀdevelopedꢀtheꢀ“AFMꢀTuningꢀAssistant”ꢀsoftware.ꢀꢀ  
YouꢀcanꢀdownloadꢀthisꢀsoftwareꢀfromꢀPhaseLink’sꢀwebꢀsiteꢀ(www.phaselink.com).ꢀꢀTheꢀsoftwareꢀconsistsꢀofꢀtwoꢀ  
worksheets.ꢀꢀTheꢀfirstꢀworksheetꢀ(namedꢀL2)ꢀisꢀusedꢀtoꢀfineꢁtuneꢀtheꢀ‘L2’ꢀinductorꢀvalue,ꢀandꢀtheꢀsecondꢀ  
worksheetꢀ(namedꢀL4)ꢀisꢀusedꢀforꢀfineꢀtuningꢀofꢀtheꢀ‘L4’ꢀ(usedꢀinꢀ4xꢀAFMsꢀonly)ꢀinductorꢀvalue.ꢀꢀꢀ  
ForꢀthoseꢀdesignsꢀusingꢀPhaseLink’sꢀrecommendedꢀboardꢀlayout,ꢀyouꢀcanꢀuseꢀtheꢀ“AFMꢀTuningꢀAssistant”ꢀtoꢀ  
determineꢀtheꢀoptimumꢀvaluesꢀforꢀtheꢀrequiredꢀinductors.ꢀꢀThisꢀsoftwareꢀisꢀdevelopedꢀbasedꢀonꢀtheꢀparasiticꢀ  
informationꢀfromꢀPhaseLink’sꢀboardꢀlayoutꢀandꢀcanꢀbeꢀusedꢀtoꢀdetermineꢀtheꢀrequiredꢀinductorꢀandꢀparallelꢀ  
capacitorꢀ(seeꢀLWB1ꢀandꢀCstrayꢀparameters)ꢀvalues.ꢀꢀForꢀthoseꢀemployingꢀaꢀdifferentꢀboardꢀlayoutꢀinꢀtheirꢀ  
design,ꢀweꢀrecommendꢀtoꢀuseꢀtheꢀparasiticꢀinformationꢀofꢀtheirꢀboardꢀlayoutꢀtoꢀcalculateꢀtheꢀoptimizedꢀinductorꢀ  
values.ꢀꢀPleaseꢀuseꢀtheꢀfollowingꢀfineꢀtuningꢀprocedure:ꢀꢀ  
47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ5ꢀꢀ  

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