PL560-69QILR PDF预览

PL560-69QILR

更新时间: 2025-10-14 03:15:27
品牌 Logo 应用领域
PLL 倍频器
页数 文件大小 规格书
15页 887K
描述
Analog Frequency Multiplier

PL560-69QILR 数据手册

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Analog Frequency Multiplier  
PL560-xx VCXO Family  
PRODUCT DESCRIPTION  
FEATURES  
NonꢁPLLꢀfrequencyꢀmultiplicationꢀ  
Inputꢀfrequencyꢀfromꢀ30ꢁ200ꢀMHzꢀꢀ  
Outputꢀfrequencyꢀfromꢀ60ꢁ800ꢀMHzꢀꢀ  
Lowꢀphaseꢀnoiseꢀandꢀjitterꢀ(equivalentꢀtoꢀfundamentalꢀ  
crystalꢀatꢀtheꢀoutputꢀfrequency)ꢀ  
PhaseLink’sꢀAnalogꢀFrequencyꢀMultiplierTMꢀ(AFM)ꢀisꢀ  
theꢀindustry’sꢀfirstꢀ‘BalancedꢀOscillator’ꢀutilizingꢀ  
analogꢀmultiplicationꢀofꢀtheꢀfundamentalꢀfrequencyꢀ  
(atꢀdoubleꢀorꢀquadrupleꢀfrequency),ꢀcombinedꢀwithꢀ  
anꢀattenuationꢀofꢀtheꢀfundamentalꢀofꢀtheꢀreferenceꢀ  
crystal,ꢀwithoutꢀtheꢀuseꢀofꢀaꢀphaseꢁlockedꢀloopꢀ  
(PLL),ꢀinꢀCMOSꢀtechnology.ꢀ  
Ultraꢁlowꢀjitterꢀ  
oRMSꢀphaseꢀjitterꢀ<ꢀ0.25ꢀpsꢀ(12kHzꢁ20MHz)ꢀ  
oRMSꢀperiodꢀjitterꢀ<ꢀ2.5ꢀpsꢀ  
Lowꢀphaseꢀnoiseꢀ  
PhaseLink’sꢀpatentꢀpendingꢀPL560ꢁxxꢀfamilyꢀofꢀAFMꢀ  
productsꢀcanꢀachieveꢀupꢀtoꢀ800ꢀMHzꢀoutputꢀ  
frequencyꢀwithꢀlittleꢀjitterꢀorꢀphaseꢀnoiseꢀ  
deterioration.ꢀꢀInꢀaddition,ꢀtheꢀlowꢀfrequencyꢀinputꢀ  
crystalꢀrequirementꢀmakesꢀtheꢀAFMsꢀtheꢀmostꢀ  
affordableꢀhighꢁperformanceꢀtimingꢁsourceꢀinꢀtheꢀ  
market.ꢀ  
oꢁ142ꢀdBc/Hzꢀ@100kHzꢀoffsetꢀfromꢀ155.52ꢀMHzꢀ  
oꢁ150ꢀdBc/Hzꢀ@10MHzꢀoffsetꢀfromꢀ155.52ꢀMHzꢀ  
Highꢀlinearityꢀpullꢀrangeꢀ(typ.ꢀ5%)ꢀ  
+/ꢁꢀ120ꢀPPMꢀpullabilityꢀVCXOꢀ  
Lowꢀinputꢀfrequencyꢀeliminatesꢀtheꢀneedꢀforꢀexpensiveꢀ  
crystalsꢀ  
Differentialꢀoutputꢀlevelsꢀ(PECL,ꢀLVDS),ꢀorꢀsingleꢁ  
endedꢀCMOSꢀꢀ  
Singleꢀ2.5Vꢀorꢀ3.3Vꢀ+/ꢁꢀ10%ꢀpowerꢀsupplyꢀ  
Optionalꢀindustrialꢀtemperatureꢀrangeꢀ(ꢁ40°Cꢀtoꢀ+85°C)ꢀꢀ  
Availableꢀinꢀ16ꢁpinꢀGREEN/RoHSꢀcompliantꢀTSSOP,ꢀ  
andꢀ3x3ꢀQFNꢀ  
PL560ꢁxxꢀfamilyꢀofꢀproductsꢀutilizeꢀlowꢁpowerꢀCMOSꢀ  
technologyꢀandꢀareꢀhousedꢀinꢀGREEN/ RoHSꢀ  
compliantꢀ16ꢁpinꢀTSSOP,ꢀandꢀ16ꢁpinꢀ3x3ꢀQFNꢀ  
packages.ꢀꢀꢀꢀ  
Figure 1: 2x AFM Phase Noise at 311.04MHz  
47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCaliforniaꢀ94538ꢀꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀwww.phaselink.com Rev.ꢀ02/09/07ꢀPageꢀ1ꢀ  

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