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PI74FCT16240TA PDF预览

PI74FCT16240TA

更新时间: 2024-10-27 23:27:39
品牌 Logo 应用领域
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页数 文件大小 规格书
6页 224K
描述
Quad 4-Bit Buffer/Driver

PI74FCT16240TA 数据手册

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PI74FCT16240T  
PI74FCT162240T  
PI74FCT162H240T  
Fast CMOS 16-Bit  
Buffer/Line Drivers  
ProductFeatures:  
Product Description:  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.6 micron CMOS technology,  
achieving industry leading speed grades.  
• PI74FCT16240T,PI74FCT162240T,andPI74FCT162H240T  
are high-speed,  
low power devices with high current drive  
• VCC =5V±10%  
• Hysteresis on all inputs  
• Packagesavailable:  
ThePI74FCT16240T,PI74FCT162240T,andPI74FCT162H240T  
are inverting 16-bit buffer/line drivers designed for applications  
driving high capacitance loads and low impedance backplanes.  
Thesehigh-speed,lowpowerdevicesofferbus/backplaneinterface  
capabilityandaflow-throughorganizationforeaseofboardlayout.  
These devices are designed with three-state controls to operate in  
a Quad-Nibble, Dual-Byte, or a single 16-bit word mode.  
–48-pin240milwideplasticTSSOP(A)  
–48-pin300milwideplasticSSOP(V)  
• High output drive: IOH = –32 mA; IOL = 64 mA  
• Power off disable outputs permit "live insertion"  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
The PI74FCT16240T output buffers are designed with a Power-  
Off disable allowing “live insertion” of boards when used as  
backplane drivers.  
The PI74FCT162240T has ±24 mA balanced output drivers. It is  
designed with current limiting resistors at its outputs to control the  
output edge rate resulting in lower ground bounce and undershoot.  
This eliminates the need for external terminating resistors for most  
interface applications.  
• Balanced output drivers: ±24 mA  
• Reduced system switching noise  
• Typical VOLP (Output Ground Bounce) < 0.6V  
atVCC =5V,TA =25°C  
The PI74FCT162H240T has “Bus Hold” which retains the input's  
last state whenever the input goes to high-impedance preventing  
“floating”inputsandeliminatingtheneedforpull-up/downresistors.  
• Bus Hold retains last active bus state during 3-state  
• Eliminates the need for external pull-up resistors  
Logic Block Diagram  
1OE  
3OE  
1A  
1A  
1A  
1A  
0
1
2
3
1
1
1
1
Y
Y
Y
Y
0
1
2
3
3
3
3
3
A
A
A
A
0
1
2
3
3
3
3
3
Y
Y
Y
Y
0
1
2
3
2OE  
4OE  
2A  
2A  
2A  
2A  
0
1
2
3
2
2
2
2
Y
Y
Y
Y
0
1
2
3
4
4
4
4
A
A
A
A
0
1
2
3
4
4
4
4
Y
Y
Y
Y
0
1
2
3
PS2030A 03/11/96  
1

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