PI74FCT16374/162374/162H374T
PI74FCT16374T
16-BIT REGISTERS (3-STATE)
PI74FCT162374T
PI74FCT162H374T
Fast CMOS 16-Bit
Registers (3-State)
ProductFeatures:
CommonFeatures:
Product Description:
• PI74FCT16374T,PI74FCT162374T,andPI74FCT162H374T
are high-speed,
low power devices with high current drive.
• Vcc=5V±10%
Pericom Semiconductor’s PI74FCT series of logic circuits are
producedintheCompany’sadvanced0.6micronCMOStechnology,
achieving industry leading speed grades.
ThePI74FCT16374T,PI74FCT162374T,andPI74FCT162H374T
are 16-bit octal registers designed with 16 D-type flip-flops with a
buffered common clock and 3-state outputs. The Output Enable
(xOE) and clock (xCLK) controls are organized to operate as
two 8-bit registers or one 16-bit register. When OE is HIGH, the
outputs are in the high impedance state. Input data meeting the
setup and hold time requirements of the D inputs is transferred to
the O outputs on the LOW-to-HIGH transition of the clock input.
• Hysteresis on all inputs
• Packagesavailable:
–48-pin240milwideplasticTSSOP(A)
–48-pin300milwideplasticSSOP(V)
PI74FCT16374TFeatures:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
• Typical VOLP (Output Ground Bounce) < 1.0V
atVCC =5V,TA =25°C
PI74FCT162374TFeatures:
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
atVCC =5V,TA =25°C
PI74FCT162H374TFeatures:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
The PI74FCT16374T output buffers are designed with a Power-Off
disable allowing “live insertion” of boards when used as backplane
drivers.
The PI74FCT162374T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H374T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down
resistors.
Logic Block Diagram
1OE
2OE
1CLK
2CLK
1D0
2D0
D
D
1O0
2O0
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
PS2034A
03/28/01
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