Datasheet > PI6C9910AH

PI6C9910AH

更新时间： 2024-10-01 20:27:55

品牌	Logo	应用领域
百利通 - PERICOM		驱动信息通信管理光电二极管逻辑集成电路
页数	文件大小	规格书
8页	241K
描述
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), BICMOS, PDSO24, 5.30 MM, 0.65 MM PITCH, SSOP-24

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PI6C9910AH 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	SSOP, SSOP24,.3
针数：	24	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.86	系列：	6C
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e0	长度：	8.2 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.024 A
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	8
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP24,.3	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	5 V
Prop。Delay @ Nom-Sup：	0.5 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.5 ns	座面最大高度：	2 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	BICMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	5.3 mm
最小 fmax：	80 MHz	Base Number Matches：	1

PI6C9910AH 数据手册

Application Note 14

Managing Clock Distribution and

Optimizing Clock Skew in Networking Applications

by Cameron Katrai

Abstract

Today’s high performance systems need low skew clock

generation and distribution. Clock skew is defined as the

difference in time between simultaneous clock transitions

within a system. The skew has become the major part of con-

straints that form the upper boundary for the system clock fre-

quency.

Clock networks must be designed to minimize skew or the

differences in delay throughout a clocking network. It is ideal

that every component, such as sequential elements, i.e. flip-

flops and latches, that need clocking, should receive the edge

of the clock at the same time within each clock period. Fully

synchronous designs require this methodology. Synchronous

designs are highly recommended since they can tolerate higher

clock rates and are easier to perform timing analysis.

Reduction in system clock skew reduces cost by avoiding com-

plicated architecture or faster logic. Phase Lock Loop-based

clock distribution is becoming one of the most sought after

solutions for creating low skew system designs. Pericom has

developed the following set of low-skew PLL Clock Drivers:

PI6C2501(3V), PI6C2308A (3V), PI6C2509A (3V),

PI6C2510 (3V), PI6C5932 (5V), PI6C9910 (5V), and

PI6C9930 (3V). They provide zero input-to-output delay

using high-speed process and phase lock loop technology. In

a 24-pin TSSOP package, the PI6C2509A supports Spread

Spectrum modulation of timing signals and operates faster and

consumes less space than alternative devices, providing

significant improvements in performance and cost.

PI6C2501(3V), PI6C2308A(3V), PI6C2509A/2510A(3V),

PI6C5932(5V), PI6C9910(5V), and PI6C9930(3V), provide

the lowest phase error over all frequencies and introduce no

additional jitter as a result of Spread Spectrum modulated in-

put clock signal. It is these features that allow Pericom’s PLL

clock drivers to support stringent input-to-output delay (150ps)

and output-to-output skew less than 200ps.

To ensure that the network operates as closely to the ideal as

possible, the skew must be minimized along the entire clock-

ing network. This ensures that all sequential elements see a

common clock edge. For any design with more than 100 flops

and latches, Pericom strongly suggests some form of clock

tree structure for clocking. Buffer delays and wiring delays

are the two most significant factors contributing to skew. The

clock topology can significantly contribute to skew. As will be

discussed, a good clock network must balance factors such as

skew and clock tree delays. In the next section a real clock

design is examined for analysis of clock skew.

Design Example

Both the delay in the data path and the clock skew affect data

transfer from one section of the design to the other sections.

The data path delay is defined as the delay from a register (F1)

in a section to the D input of another register (F2). Figure 1

depicts this delay. The delay includes CLKA to Q1 and set up

hold time at point B.

Introduction

The clock skew or Tskew is the difference between a rising

edge on CLKA in F1 and CLKB in F2. The Tskew defines

both the positive and negative skew. Positive skew affects data

transfer from a hold time standpoint. Negative skew affects data

transfer from a set up time standpoint. If the data path from F1

to F2 is too long, a set up time violation is realized on F2.

Clock skews also affect the set up and hold time. A more

practical and realistic clock distribution is shown in Figure 2.

Better Clock distribution strategies using PLL clock drivers

have made a significant contribution to high-performance

system design. If clock distribution networks are not properly

constructed, they may detract from system-level performance.

This application note defines the skew in a system, describing

its effect on performance. Recommendation and supporting

analysis are given for designing near optimal clock networks.

This note also illustrates that clock network design can be a

surprisingly complex task involving many tradeoffs.

12/29/98

12 3 4 5 6 7 8

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与PI6C9910AH相关器件

型号	品牌	获取价格	描述	数据表
PI6C9910AHX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 5.30 MM
PI6C9910AS	ETC	获取价格	Eight Distributed-Output Clock Driver
PI6C9910ASX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 I
PI6C9910H	ETC	获取价格	Eight Distributed-Output Clock Driver
PI6C9910S	ETC	获取价格	Eight Distributed-Output Clock Driver
PI6C9911	PERICOM	获取价格	5V High-Speed Programmable Skew Clock Buffers
PI6C9911-2	PERICOM	获取价格	Clock IC \| 250ps Accuracy. 5V. TTL. 3.75 to 100 MHz
PI6C9911-2I	ETC	获取价格	Eight Distributed-Output Clock Driver
PI6C9911-2J	PERICOM	获取价格	5V High-Speed Programmable Skew Clock Buffers
PI6C9911-2JX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC

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