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PI6C9910AS PDF预览

PI6C9910AS

更新时间: 2024-09-30 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟驱动器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
6页 273K
描述
Eight Distributed-Output Clock Driver

PI6C9910AS 数据手册

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PI6C9910  
Zero-Delay Clock Buffer  
Features  
Description  
• Zero input to output delay  
• Eight clock copies from one clock input  
• 15 - 80 MHz output operation  
• Fifty percent duty cycle  
The PI6C9910 is a low-skew clock driver designed to simplify  
clockdistributioninsystemsrequiringnearsynchronousclocks. A  
typical application is in SDRAM modules. Each of the eight  
outputs (Q0-Q7) can drive individual 50transmission lines with  
minimal distortion or skew, and full 5V swing.  
• Low skew (< 250ps typ.)  
An on-chip phase-locked loop (PLL) synchronizes the feedback  
(FB)tothereference(REF)input, achieving“zero-delay”buffered  
outputs.  
• V = 5.0V +/- 10%, T = 0° to 70°  
• Low jitter (< 250 ps cycle to cycle), < 60ps RMS  
• Low noise unbalanced drive outputs (PI6C9910-5)  
CC  
A
• Low noise balanced drive outputs (PI6C9910A)  
• Packagesavailable:  
InsertinganexternalcounterbetweenanyoftheQxoutputsandthe  
FB pin allows for generation of eight synchronous clock copies  
whose frequency is a multiple of a lower frequency REF input.  
–24-pin300milwideSOIC(S)  
–24-pin209milwideSSOP(H)  
• CompatiblewithCypressCY7B9910-5  
The voltage-controlled oscillator (VCO) frequency is determined  
by the filtered ouput coming from the Phase/Frequency Detector.  
The frequency select (FS) input sets the VCO operating range.  
Test Mode  
PI6C9910-5 has unbalanced output drivers (TTL), and is fully  
compatiblewiththeCypressCY7B9910-5.ThePI6C9910Afeatures  
balanced-drive outputs (CMOS) for improved rise/fall time  
symmetry.  
In normal operation the TEST pin is tied to ground. For testing  
purposes it can have a removable jumper to ground or a 100Ω  
pull-down resistor. When the TEST pin is driven HIGH, the VCO  
output is disconnected, and all eight outputs (Q0-Q7) are directly  
driven from the REF input.  
The FS and TEST inputs have internal pull-up resistors.  
Block Diagram  
Pinout  
REF  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
GND  
TEST  
NC  
V
CCQ  
FS  
NC  
GND  
V
CCQ  
V
CCN  
24-Pin  
S, H  
V
Q7  
Q6  
GND  
Q5  
Q4  
CCN  
Q0  
Q1  
GND  
Q2  
9
10  
11  
12  
Q3  
V
CCN  
FB  
V
CCN  
PS8341B 03/05/99  
108  

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