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PI6C487016FBE PDF预览

PI6C487016FBE

更新时间: 2024-09-30 06:03:11
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器
页数 文件大小 规格书
8页 426K
描述
Low Skew, 1-to-16 LVCMOS / LVTTL Clock Driver

PI6C487016FBE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.83
系列:6C输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.002 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8/3.3,3.3 V
Prop。Delay @ Nom-Sup:4.7 ns传播延迟(tpd):4.7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.17 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN (787)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mm

PI6C487016FBE 数据手册

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PI6C487016  
Low Skew, 1-to-16  
LVCMOS / LVTTL Clock Driver  
Product Description  
Product Features  
The PI6C487016 is a low skew. 1:16 LVCMOS/LVTTL Clock  
Driver. The device has 4 banks of 4 outputs and each bank can  
be independently selected for ÷1 or ÷2 frequency operation.  
Each bank also has its own power supply pins so that the banks  
can operate at the following different voltage levels: 3.3V, 2.5V,  
and 1.8V. The low impedance LVCMOS/LVTTL outputs are  
designed to drive 50Ω series or parallel terminated transmission  
lines.  
16 LVCMOS/LVTTL outputs (4 banks of 4 outputs)  
• Selectable differential or single-ended clock inputs  
• CLK1, nCLK1 pair can accept the following differential input  
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• CLK0 supports the following input types: LVCMOS, LVTTL  
• Maximum output frequency: 250MHz  
• Independent bank control for ÷1 or ÷2 operation  
The divide select inputs, SELA:SELD, control the output fre-  
quency of each bank with either ÷1 or ÷2 frequency operation.  
The bank enable inputs, ENA:END, support enabling and dis-  
abling each bank of outputs individually. The outputs synchro-  
nized when enabling or disabling the clock outputs. The master  
reset input nMR/OE, resets the ÷1/÷2 flip flops and also controls  
the active and high impedance states of all outputs.  
• Independent output bank voltage settings for 3.3V, 2.5V, or  
1.8V operations  
• Output skew: 170ps (max)  
• Bank skew: 50ps (max)  
• Part-to-part skew: 800ps (max)  
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply  
• -40° to +85°C ambient operating temperature  
The PI6C487016 is characterized to operate with the core at  
3.3V and the output banks at 3.3V, 2.5V or 1.8V.  
• Available packages:  
-Pb-free & green 48-pin LQFP(FB)  
Pin Description  
Block Diagram  
nMR/OE  
D
CLK0  
4
4
0
1
1
0
QA0:QA3  
QB0:QB3  
QC0:QC3  
QD0:QD3  
÷1  
÷2  
48 47 46 45 44 43 42 41 40 39 38 37  
LE  
VDD  
CLK0  
SELA  
SELB  
SELC  
SELD  
ENA  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
QB0  
CLK1  
nCLK1  
2
D
3
4
VDDOB  
QB1  
1
0
CLK_SEL  
LE  
5
GND  
QB2  
SELA  
SELB  
SELC  
SELD  
D
6
7
4
4
1
0
LE  
VDDOB  
QB3  
ENB  
8
D
ENC  
END  
9
GND  
QC0  
VDDOC  
QC1  
1
0
10  
11  
12  
LE  
ENA  
ENB  
nMR/OE  
GND  
13 14 15 16 17 18 19 20 21 22 23 24  
ENC  
END  
PS8741D  
07/29/05  
1

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