Datasheet > PI6C49003

PI6C49003

更新时间： 2024-10-01 01:19:35

品牌	Logo	应用领域
百利通 - PERICOM		/
页数	文件大小	规格书
12页	289K
描述
Networking Clock Generator

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中文翻译

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数据手册

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PI6C49003 数据手册

PI6C49003

Networking Clock Generator

Description

Features

The PI6C49003 is a clock generator device intended for PCIe®/

networking applications. The device includes ﬁve 100MHz

differential Host Clock Signal Level (HCSL) outputs for PCIe,

two single-ended 50 MHz outputs, one single-ended 32.256MHz

output, and one selectable single-ended 33/66/133 MHz output.

• 3.3V +/-10% Supply Voltage

• Uses 25MHz xtal such as Saronix-eCera™ SRX7278

• Five PCIe® 100MHz outputs with optional -0.5% spread

spectrum support

• Two LVCMOS 50MHz outputs that support +/- 10%

frequency margining

Using a serially programmable SMBUS interface, the PI6C49003

incorporates spread spectrum modulation on the ﬁve 100 MHz

HCSL PCIe outputs, and independent frequency margining on the

50MHz output, 33.3333MHz and 66.6666MHz clock outputs.

• One frequency selectable 33/66/133MHz LVCMOS output

• One 32.256MHz LVCMOS output

• Industrial temperature -40°C to 85°C

• Package: 48-pin TSSOP package

Pin Conﬁguration

VDD

IREF

GND

VDD

100M_Q0-

100M_Q0+

100M_Q1+

100M_Q1-

VDD

GND

VDD

GND

VDD

Block Diagram

100M_Q2+

100M_Q2-

100M_Q3+

100M_Q3-

VDD

SCLK

SDATA

GND

25 MHz

Clock Buffer/

crystal or

Crystal

Oscillator

clock input

100M_OUT(0-4)

50M_Out1

50M_Out2

VDD

GND

VDD

50M_OUT(1-2)

100M_Q4+

100M_Q4-

33/66/133M_Out1

VDD

PLL, Dividers,

Buffers, and

Logic

GND

33/66/133M_OUT1

VDD

32.256M_Out1

GND

SCLK

32.256M_OUT1

SDATA

GND

PD_RESET

VDD

PD_RESET

ISET

475 Ohms

GND

PS9023A

11/20/09

09-0097

12 3 4 5 6 7...12

中文翻译

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