PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Description
Features
TheꢀPI6C49004AꢀisꢀaꢀclockꢀgeneratorꢀdeviceꢀintendedꢀforꢀPCIe®ꢀ
Gen2ꢀ networkingꢀ applications.ꢀ Theꢀ deviceꢀ includesꢀ twelveꢀ
100MHzꢀ differentialꢀ Hostꢀ Clockꢀ Signalꢀ Levelꢀ (HCSL)ꢀ outputsꢀ
forꢀPCIeꢀGenꢀ2,ꢀtwoꢀsingle-endedꢀ50MHzꢀoutputs,ꢀoneꢀsingle-
endedꢀ 32.256MHzꢀ output,ꢀ andꢀ oneꢀ selectableꢀ single-endedꢀ
33/66/133MHzꢀoutput.
•ꢀ 3.3Vꢀ+/-10%ꢀSupplyꢀVoltage
•ꢀ Usesꢀ25MHzꢀxtalꢀsuchꢀasꢀSaronix-eCera™ꢀSRX7278
•ꢀ TwelveꢀPCIe®ꢀGen.ꢀ2ꢀ100MHzꢀHCSLꢀoutputsꢀwithꢀoptionalꢀ
-0.5%ꢀspreadꢀspectrumꢀsupportꢀ
•ꢀ TwoꢀLVCMOSꢀ50MHzꢀoutputsꢀthatꢀsupportꢀ+/-ꢀ10%ꢀ
frequencyꢀmargining
UsingꢀaꢀseriallyꢀprogrammableꢀSMBUSꢀinterface,ꢀtheꢀPI6C49004Aꢀ
incorporatesꢀspreadꢀspectrumꢀmodulationꢀonꢀtheꢀtwelveꢀ100MHzꢀ
HCSLꢀPCIeꢀGenꢀ2ꢀoutputs,ꢀandꢀindependentꢀfrequencyꢀmarginingꢀ
onꢀ theꢀ 50MHzꢀ output,ꢀ 33.3333MHzꢀ andꢀ 66.6666MHzꢀ clockꢀ
outputs.
•ꢀ Oneꢀfrequencyꢀselectableꢀ33/66/133MHzꢀLVCMOSꢀoutput
•ꢀ Oneꢀ32.256MHzꢀLVCMOSꢀoutput
•ꢀ Industrialꢀtemperatureꢀ-40°Cꢀtoꢀ85°C
•ꢀ Package:ꢀ56-pinꢀTSSOPꢀpackage
Pin Configuration
VDD
IREF
1
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
VDD
NC
3
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
100M_Q11-
100M_Q11+
100M_Q10-
100M_Q10+
VDD
4
5
6
7
8
GND
VDD
9
VDD
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
100M_Q4+
100M_Q4-
100M_Q5+
100M_Q5-
VDD
100M_Q9-
100M_Q9+
100M_Q8-
100M_Q8+
100M_Q7-
100M_Q7+
SCLK
Block Diagram
VDD
12
25 MHz
Clock Buffer/
crystal or
Crystal
12
2
SDATA
clock input
Oscillator
100M_OUT(0-11)
GND
GND
50M_OUT1
50M_OUT2
VDD
VDD
50M_OUT(1-2)
PLL, Dividers,
Buffers, and
Logic
100M_Q6+
100M_Q6-
33/66/133M_OUT1
VDD
33/66/133M_OUT1
GND
SCLK
32.256M_OUT1
VDD
SDATA
PD_RESET
32.256M_OUT1
GND
GND
VDD
NC
X2
8
PD_RESET
X1
ISET
475 Ohms
1%
GND
PS-01
04/19/11
11-0104
1