Datasheet > PI6C49003A

PI6C49003A

更新时间： 2024-10-01 01:19:35

品牌	Logo	应用领域
百利通 - PERICOM		PC
页数	文件大小	规格书
12页	843K
描述
PCIe Gen 2 Networking Clock Generator

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中文翻译

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数据手册

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PI6C49003A 数据手册

PI6C49003A

PCIe®ꢀGen 2 Networking Clock Generator

Description

Features

TheꢀPI6C49003AꢀisꢀaꢀclockꢀgeneratorꢀdeviceꢀintendedꢀforꢀPCIe®ꢀ

Gen2ꢀnetworkingꢀapplications.ꢀTheꢀdeviceꢀincludesꢀﬁveꢀ100MHzꢀ

differentialꢀHostꢀClockꢀSignalꢀLevelꢀ(HCSL)ꢀoutputsꢀforꢀPCIeꢀGenꢀ

2,ꢀtwoꢀsingle-endedꢀ50MHzꢀoutputs,ꢀoneꢀsingle-endedꢀ32.256MHzꢀ

output,ꢀandꢀoneꢀselectableꢀsingle-endedꢀ33/66/133MHzꢀoutput.

•ꢀ 3.3Vꢀ+/-10%ꢀSupplyꢀVoltage

•ꢀ Usesꢀ25MHzꢀxtalꢀ

•ꢀ FiveꢀPCIe®ꢀGen.ꢀ2ꢀ100MHzꢀHCSLꢀoutputsꢀwithꢀoptionalꢀ

-0.5%ꢀspreadꢀspectrumꢀsupportꢀ

•ꢀ TwoꢀLVCMOSꢀ50MHzꢀoutputsꢀthatꢀsupportꢀ+/-ꢀ10%ꢀ

frequencyꢀmargining

UsingꢀaꢀseriallyꢀprogrammableꢀSMBUSꢀinterface,ꢀtheꢀPI6C49003Aꢀ

incorporatesꢀspreadꢀspectrumꢀmodulationꢀonꢀtheꢀtwelveꢀ100MHzꢀ

HCSLꢀPCIeꢀGenꢀ2ꢀoutputs,ꢀandꢀindependentꢀfrequencyꢀmarginingꢀ

onꢀ theꢀ 50MHzꢀ output,ꢀ 33.3333MHzꢀ andꢀ 66.6666MHzꢀ clockꢀ

outputs.

•ꢀ Oneꢀfrequencyꢀselectableꢀ33/66/133MHzꢀLVCMOSꢀoutput

•ꢀ Oneꢀ32.256MHzꢀLVCMOSꢀoutput

•ꢀ Industrialꢀtemperatureꢀ-40°Cꢀtoꢀ85°C

•ꢀ Package:ꢀ48-pinꢀTSSOPꢀpackage

Pin Conﬁguration

Block Diagram

VDD

IREF

GND

VDD

100M_Q0-

100M_Q0+

100M_Q1+

100M_Q1-

VDD

25 MHz

Clock Buffer/

crystal or

VDD

GND

Crystal

clock input

Oscillator

100M_OUT(0-4)

GND

50M_OUT(1-2)

PLL, Dividers,

Buffers, and

Logic

VDD

GND

VDD

100M_Q2+

100M_Q2-

100M_Q3+

100M_Q3-

VDD

33/66/133M_OUT1

VDD

SCLK

32.256M_OUT1

SDATA

GND

PD_RESET

50M_Out1

50M_Out2

VDD

GND

VDD

100M_Q4+

100M_Q4-

33/66/133M_Out1

VDD

ISET

475 Ohms

GND

VDD

32.256M_Out1

GND

VDD

PD_RESET

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中文翻译

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