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PI6C410A PDF预览

PI6C410A

更新时间: 2024-11-17 10:12:59
品牌 Logo 应用领域
百利通 - PERICOM 晶体时钟发生器微控制器和处理器外围集成电路光电二极管PC
页数 文件大小 规格书
16页 712K
描述
Clock Generator for Intel PCI-Express Desktop Chipset

PI6C410A 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP56,.3,20针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.86
Is Samacsys:NJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
湿度敏感等级:1端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:400 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):235电源:3.3 V
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:500 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

PI6C410A 数据手册

 浏览型号PI6C410A的Datasheet PDF文件第2页浏览型号PI6C410A的Datasheet PDF文件第3页浏览型号PI6C410A的Datasheet PDF文件第4页浏览型号PI6C410A的Datasheet PDF文件第5页浏览型号PI6C410A的Datasheet PDF文件第6页浏览型号PI6C410A的Datasheet PDF文件第7页 
PI6C410  
Clock Generator for Intel PCI-Express Desktop Chipset  
Product Features  
Product Description  
• 14.318 MHz Crystal Input  
PI6C410 is a high-speed, low-noise clock generator designed to  
work with Intel Desktop PCI-Express Chipset.  
Spread Spectrum PLL based clock generator reduce EMI emis-  
sion and support a wide range of frequencies.  
• Selectable of 100, 133, 166, 200, 266, 333, and 400MHz CPU  
Output Frequencies  
• SMBus: Power Management Control  
• Spread Spectrum support (-0.5% down spread)  
Jitter Performance  
• < 85ps Cycle to Cycle CPU clock jitter  
• < 350ps Cycle to Cycle 48MHz clock jitter  
• < 500ps Cycle to Cycle PCI clock jitter  
• < 125ps Cycle to Cycle SRC clock jitter  
• < 1000ps Cycle to Cycle REF clock jitter  
• Packaging (Pb-free & Green available):  
-56-Pin SSOP (V)  
-56-Pin TSSOP (A)  
Output Features  
Skew Performance  
• Two Pairs of Differential CPU Clocks  
• One selectable of CPU/SRC Clock  
• Six Pairs of SRC Clocks  
• Nine PCI Clocks  
• < 100ps Output to output CPU clock skew  
• < 500ps Output to output PCI clock skew  
• < 250ps Output to output SRC clock skew  
• One 48 MHz USB clock  
• One REF clock  
• One 96 MHz Differential clock  
Pin Description  
Logic Block Diagram  
DOT_96  
DOT 96#  
XTAL_IN  
XTAL  
OSC  
PLL 2  
VDD_PCI  
VSS_PCI  
PCI_3  
PCI_4  
PCI_5  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
PCI_2  
PCI_1  
PCI_0  
FS_C / TEST_SEL  
REF  
VSS_REF  
XTAL_IN  
XTAL_OUT  
VDD_REF  
SDA  
SCL  
VSS_CPU  
CPU_0  
XTAL_OUT  
USB_48  
REF  
/2  
PLL 1  
VSS_PCI  
VDD_PCI  
PCIF_0 / ITP_EN  
PCIF_1  
PCI [0:5]  
PCIF[0:2]  
Div  
SDA  
SCL  
SMBus  
Logic  
9
PCIF_2  
VDD_48  
USB_48  
VSS_48  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
SRC [1:6]  
SRC [1:6]#  
Div  
Div  
FS_A  
C
O
N
T
R
O
L
DOT_96  
CPU_0#  
VDD_CPU  
CPU_1  
CPU_1#  
IREF  
DOT_96#  
FS_B / TEST_MODE  
VTT_PWRGD# / PWRDWN  
FS_A  
CPU2_ITP / SRC7  
CPU2_ITP# / SRC7#  
FS_B / TEST_MODE  
FS_C / TEST_SEL  
CPU[0:1]  
CPU[0:1]#  
SRC_1  
SRC_1#  
VDD_SRC  
SRC_2  
SRC_2#  
SRC_3  
SRC_3#  
SRC_4  
SRC_4#  
VSS_A  
VDD_A  
VTT_PWRGD#  
/ PWRDWN  
CPU2_ITP / SRC7  
CPU2_ITP# / SRC7#  
VDD_SRC  
SRC_6  
SRC_6#  
SRC_5  
PCIF_0 / ITP_EN  
SRC_5#  
VSS_SRC  
VDD_SRC  
PS8734A  
09/02/04  
1

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