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PI3WVR12612NEE PDF预览

PI3WVR12612NEE

更新时间: 2024-11-06 21:17:27
品牌 Logo 应用领域
美台 - DIODES /
页数 文件大小 规格书
1页 401K
描述
Audio/Video Switch,

PI3WVR12612NEE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:not_compliant
ECCN代码:EAR99风险等级:8.45
模拟集成电路 - 其他类型:AUDIO/VIDEO SWITCH峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

PI3WVR12612NEE 数据手册

  
New Product Brief  
PI3WVR12612  
Wide Voltage Range DisplayPort™ & HDMI Video Switch  
Pericom Semiconductor’s PI3WVR12612 is a multi-standard  
Features  
video switch with wide voltage range capability. It supports  
DisplayPort 1.2, HDMI 1.4, and emerging and proprietary  
Î4-lane, 1:2 mux/demux that will support RBR,  
standards.  
HBR1, or HBR2  
PI3WVR12612 can pass high-speed signals up to 1.2V  
peak-to-peak differential with a common-mode voltage from  
0 to 3.4V. The wide voltage range allows DC-coupled multi-  
standard operation. Eliminating AC coupling capacitors  
saves board space and improves signal integrity for dense  
PCB designs.  
Î1-channel 1:2 mux/demux for HPD signal  
ÎDifferential switch matrix for DP AUX and HDMI DDC  
ÎSupports 720 Mbps high-speed DP AUX  
Î-1.8 dB Insertion Loss for Dx channels @ 2.7 GHz  
Î-3 dB Bandwidth for Dx channels: 4.1 GHz  
ÎReturn loss for Dx channels @ 2.7GHz: -14 dB  
In addition to four high-speed lanes, PI3WVR12612 also  
switches AUX, DDC, and HPD signals.  
Application  
Routing of DisplayPort and HDMI signals with low signal at-  
tenuation between source and sink.  
ÎLow Crosstalk for high speed channels:  
-28 dB@5.4 Gbps  
ÎLow Off Isolation for high speed channels:  
PI3WVR12612  
Video Source 1  
-22dB@5.4 Gbps  
4
DIN1_n+  
0
4
DIN1_n+  
DOUT_  
DOUT_  
4
DIN2_n+  
DIN2_n+  
1
Flat Panel  
HDTV  
ÎLow channel-to-channel skew, 35ps max  
ÎLow Bit-to-Bit Skew, 5ps typ (between '+' and '-' bits)  
ÎVDD Operating Range: 3.3V +/-10%  
ÎESD Tolerance: 2kV HBM  
DAUX1+  
00  
10  
DAUX1-  
DAUX2+  
DAUX2-  
AUX+  
AUX-  
AUX+  
AUX-  
Video Source 2  
SCL  
SDA  
CAB_B  
HPDIN  
HPD_1  
HPD_2  
0
1
SPU_SEL  
CAB_A  
ÎPackaging (Pb-free & Green): 50 BGA (NEE)  
Block Diagram  
D0+  
D0-  
D1+  
D1-  
D0+A  
D0-A  
D1+A  
D1-A  
AUX+  
AUX+A  
AUX+B  
SCL_A  
SCL_B  
SCL  
D2+  
D2-  
D3+  
D3-  
D2+A  
D0-A  
D3+A  
D3-A  
AUX-  
AUX-A  
AUX-B  
SDA_A  
SDA_B  
D0+B  
D0-B  
D1+B  
D1-B  
SDA  
HPD  
D2+B  
D2-B  
D3+B  
D3-B  
HPD  
HPD  
A
B
DDC_AUX_SEL  
GPU_SEL  
OE  
Logic  
Control  

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