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PEEL22CV10AZSI-25L PDF预览

PEEL22CV10AZSI-25L

更新时间: 2024-11-16 14:44:11
品牌 Logo 应用领域
美台 - DIODES 时钟输入元件光电二极管可编程逻辑
页数 文件大小 规格书
10页 490K
描述
EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.300 INCH, LEAD FREE, SOIC-24

PEEL22CV10AZSI-25L 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP24,.4
针数:24Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.15
Is Samacsys:N架构:PAL-TYPE
最大时钟频率:33.3 MHzJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:15.4 mm
湿度敏感等级:3专用输入次数:11
I/O 线路数量:10输入次数:22
输出次数:10产品条款数:133
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
可编程逻辑类型:EE PLD传播延迟:25 ns
认证状态:Not Qualified座面最大高度:2.64 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

PEEL22CV10AZSI-25L 数据手册

 浏览型号PEEL22CV10AZSI-25L的Datasheet PDF文件第2页浏览型号PEEL22CV10AZSI-25L的Datasheet PDF文件第3页浏览型号PEEL22CV10AZSI-25L的Datasheet PDF文件第4页浏览型号PEEL22CV10AZSI-25L的Datasheet PDF文件第5页浏览型号PEEL22CV10AZSI-25L的Datasheet PDF文件第6页浏览型号PEEL22CV10AZSI-25L的Datasheet PDF文件第7页 
Notrecommendedfor Newdesigns-  
contactfactoryforavailability
PEEL™ 22CV10AZ-25  
CMOS Programmable Electrically Erasable Logic Device  
Architectural Flexibility  
Features  
-
133 product terms x 44 input AND array  
Ultra Low Power Operation  
-
-
-
-
-
-
Up to 22 inputs and 10 I/O pins  
- IcCcC= 10 µA (typical) at standby  
- V = 5 Volts ±10%  
12 possible macrocell configurations  
Synchronous preset, asynchronous clear  
Independent output enables  
- Icc = 2 mA (typical) at 1 MHz  
- tPD = 25ns.  
Programmable clock source and polarity  
24-pin DIP/SOIC/TSSOP and 28-pin PLCC  
CMOS Electrically Erasable Technology  
- Superior factory testing  
-
Reprogrammable in plastic package  
Reduces retrofit and development costs  
Application Versatility  
-
-
-
-
Replaces random logic  
Pin and JEDEC compatible with 22V10  
Ideal for power-sensitive systems  
Development/Programmer Support  
- Third party software and programmers  
- Anachip PLACE Development Software  
General Description  
The PEEL™22CV10AZ is JEDEC file compatible with standard  
22V10 PLDs. Eight additional configurations per macrocell (a  
total of 12) are also available by using the “+” software/program-  
ming option (i.e., 22CV10AZ+ & 22CV10AZ++). The additional  
macrocell configurations allow more logic to be put into every  
device, potentially reducing the design's component count and  
lowering the power requirements even further.  
The PEEL™22CV10AZ is a Programmable Electrically Erasable  
Logic (PEEL™) device that provides a low power alternative to  
ordinary PLDs. The PEEL™22CV10AZ is available in 24-pin  
DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A  
“zero-power” (100µA max. ICC) standby mode makes the  
PEEL™22CV10AZ ideal for power sensitive applications such as  
handheld meters, portable communication equipment and lap- top  
computers/ peripherals. EE-reprogrammability provides the  
convenience of instant reprogramming for development and a  
reusable production inventory minimizing the impact of pro-  
gramming changes or errors. EE-reprogrammability also  
improves factory testability, thus ensuring the highest quality  
possible.  
Development  
and  
programming  
support  
for  
the  
PEEL™22CV10AZ is provided by popular third-party program-  
mers and development software. Anachip also offers free Win-  
PLACE development software.  
Figure 19 Block Diagram  
Figure 19 Pin Configuration  
I/CLK  
1
24  
VCC  
I
I
2
3
23  
22  
I/O  
I/O  
I
I
4
5
21  
20  
I/O  
I/O  
I
I
6
7
19  
18  
I/O  
I/O  
I
I
I
8
17  
16  
15  
I/O  
I/O  
I/O  
9
10  
I
11  
12  
14  
13  
I/O  
I
GND  
TSSOP  
DIP  
PLCC  
SOIC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  

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