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PDU53-1000M PDF预览

PDU53-1000M

更新时间： 2024-02-10 01:17:04
品牌 Logo 应用领域
DATADELAY 延迟线光电二极管
页数 文件大小 规格书
4页 251K
描述
3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)

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PDU53-1000M 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：0.600 INCH, DIP-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.14JESD-30 代码：R-XDIP-T16
JESD-609代码：e3长度：22.098 mm
逻辑集成电路类型：ACTIVE DELAY LINE功能数量：1
抽头/阶步数：7端子数量：16
输出特性：OPEN-EMITTER输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED可编程延迟线：YES
认证状态：Not Qualified座面最大高度：10.033 mm
表面贴装：NO技术：ECL
端子面层：Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总延迟标称（td）：7 ns
宽度：15.24 mmBase Number Matches：1

PDU53-1000M 数据手册

 浏览型号PDU53-1000M的Datasheet PDF文件第2页浏览型号PDU53-1000M的Datasheet PDF文件第3页浏览型号PDU53-1000M的Datasheet PDF文件第4页 
PDU53  
3-BIT, ECL-INTERFACED  
PROGRAMMABLE DELAY LINE  
(SERIES PDU53)  
FEATURES  
PACKAGES  
N/C  
16  
15  
14  
13  
12  
11  
10  
9
IN  
A2  
A1  
VEE  
A0  
N/C  
N/C  
N/C  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
IN  
N/C  
N/C  
•
•
•
•
•
Digitally programmable in 8 delay steps  
Monotonic delay-versus-address variation  
Precise and stable delays  
Input & outputs fully 100K-ECL interfaced & buffered  
Available in 16-pin DIP (600 mil) socket or SMD  
A2  
N/C  
GND  
OUT  
N/C  
N/C  
N/C  
A1  
GND  
OUT  
N/C  
VEE  
A0  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
PDU53-xx DIP  
PDU53-xxC3 SMD  
PDU53-xxM Military DIP PDU53-xxMC3 Mil SMD  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The PDU53-series device is a 3-bit digitally programmable delay line. The  
delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the  
address code (A2-A0) according to the following formula:  
IN  
Signal Input  
OUT Signal Output  
A2  
A1  
A0  
Address Bit 2  
Address Bit 1  
Address Bit 0  
TDA = TD0 + TINC * A  
VEE -5 Volts  
GND Ground  
where A is the address code, TINC is the incremental delay of the device,  
and TD0 is the inherent delay of the device. The incremental delay is  
specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The  
address is not latched and must remain asserted during normal operation.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
•
Total programmed delay tolerance: 5% or 40ps,  
Part  
Incremental Delay  
Per Step (ps)  
100 ± 50  
Total Delay  
Change (ns)  
0.70  
whichever is greater  
Number  
PDU53-100  
PDU53-200  
PDU53-250  
PDU53-400  
PDU53-500  
PDU53-750  
PDU53-1000  
PDU53-1200  
PDU53-1500  
PDU53-2000  
PDU53-2500  
PDU53-3000  
•
•
•
•
•
•
•
Inherent delay (TD0): 2.2ns typical  
Address to input setup (TAIS): 2.9ns  
Operating temperature: 0° to 85° C  
Temperature coefficient: 100PPM/°C (excludes TD0)  
Supply voltage VEE: -5VDC ± 0.7V  
Power Supply Current: -150ma typical (50Ω to -2V)  
Minimum pulse width: 3ns or 15% of total delay,  
whichever is greater  
1.40  
200 ± 60  
1.75  
250 ± 60  
2.80  
400 ± 80  
3.50  
500 ± 100  
750 ± 100  
5.25  
7.00  
1000 ± 200  
1200 ± 200  
1500 ± 200  
2000 ± 400  
2500 ± 400  
3000 ± 500  
8.40  
10.50  
14.00  
17.50  
21.00  
•
Minimum period: 8ns or 2 x pulse width, whichever  
is greater  
A2-A0  
A i-1  
Ai  
NOTE: Any dash number between 100 and 3000  
not shown is also available.  
PWIN  
TOAX  
TAIS  
IN  
TDA  
PWOUT  
OUT  
Figure 1: Timing Diagram  
1997 Data Delay Devices  
Doc #98003  
3/18/98  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  
1234

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