Datasheet > PDU53-1000M

PDU53-1000M

更新时间： 2024-02-08 13:25:34

品牌	Logo	应用领域
DATADELAY		延迟线光电二极管
页数	文件大小	规格书
4页	251K
描述
3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)

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PDU53-1000M 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	0.600 INCH, DIP-16	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.14	JESD-30 代码：	R-XDIP-T16
JESD-609代码：	e3	长度：	22.098 mm
逻辑集成电路类型：	ACTIVE DELAY LINE	功能数量：	1
抽头/阶步数：	7	端子数量：	16
输出特性：	OPEN-EMITTER	输出极性：	TRUE
封装主体材料：	UNSPECIFIED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	可编程延迟线：	YES
认证状态：	Not Qualified	座面最大高度：	10.033 mm
表面贴装：	NO	技术：	ECL
端子面层：	Tin (Sn)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	总延迟标称（td）：	7 ns
宽度：	15.24 mm	Base Number Matches：	1

PDU53-1000M 数据手册

PDU53

APPLICATION NOTES

conditions are those for which the delay

ADDRESS UPDATE

tolerance specifications and monotonicity are

guaranteed. The suggested conditions are

those for which signals will propagate through the

unit without significant distortion. The absolute

conditions are those for which the unit will

produce some type of output for a given input.

The PDU53 is a memory device. As such,

special precautions must be taken when

changing the delay address in order to prevent

spurious output signals. The timing restrictions

are shown in Figure 1.

When operating the unit between the

After the last signal edge to be delayed has

appeared on the OUT pin, a minimum time, T_OAX

is required before the address lines can change.

This time is given by the following relation:

recommended and absolute conditions, the

delays may deviate from their values at low

frequency. However, these deviations will

remain constant from pulse to pulse if the input

pulse width and period remain fixed. In other

words, the delay of the unit exhibits frequency

and pulse width dependence when operated

beyond the recommended conditions. Please

consult the technical staff at Data Delay Devices

if your application has specific high-frequency

requirements.

T_OAX= max { (A_i- A _i-1) * T_INC, 0 }

where A _i-1and A_iare the old and new address

codes, respectively. Violation of this constraint

may, depending on the history of the input signal,

cause spurious signals to appear on the OUT

pin. The possibility of spurious signals persists

until the required T_OAXhas elapsed.

Please note that the increment tolerances listed

represent a design goal. Although most delay

increments will fall within tolerance, they are not

guaranteed throughout the address range of the

unit. Monotonicity is, however, guaranteed over

all addresses.

INPUT RESTRICTIONS

There are three types of restrictions on input

pulse width and period listed in the AC

Characteristics table. The recommended

PACKAGE DIMENSIONS

16 15 14 13 12 11 10

.600

±.00

.580

MAX.

.010

±.002

.870±.010

Lead Material:

Nickel-Iron alloy 42

TIN PLATE

.380

MAX.

.015 TYP.

.070 MAX.

.018

TYP.

.700±.010

7 Equal spaces

each .100±.010

Non-Accumulative

PDU53-xx (Commercial DIP)

PDU53-xxM (Military DIP)

Doc #98003

3/18/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

123 4

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与PDU53-1000M相关器件

型号	品牌	描述	获取价格	数据表
PDU-53-1000MC3	DATADELAY	ACTIVE DELAY LINE, TRUE OUTPUT, DSO16	获取价格
PDU53-1000MC3	DATADELAY	3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)	获取价格
PDU53-100C3	DATADELAY	3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)	获取价格
PDU-53-100M	DATADELAY	ACTIVE DELAY LINE, TRUE OUTPUT, DIP16, DIP-16	获取价格
PDU53-100M	DATADELAY	3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)	获取价格
PDU-53-100MC3	DATADELAY	ACTIVE DELAY LINE, TRUE OUTPUT, DSO16	获取价格

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