5秒后页面跳转
PDU53-1000M PDF预览

PDU53-1000M

更新时间: 2024-01-06 18:46:13
品牌 Logo 应用领域
DATADELAY 延迟线光电二极管
页数 文件大小 规格书
4页 251K
描述
3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)

PDU53-1000M 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:0.600 INCH, DIP-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.14JESD-30 代码:R-XDIP-T16
JESD-609代码:e3长度:22.098 mm
逻辑集成电路类型:ACTIVE DELAY LINE功能数量:1
抽头/阶步数:7端子数量:16
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED可编程延迟线:YES
认证状态:Not Qualified座面最大高度:10.033 mm
表面贴装:NO技术:ECL
端子面层:Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总延迟标称(td):7 ns
宽度:15.24 mmBase Number Matches:1

PDU53-1000M 数据手册

 浏览型号PDU53-1000M的Datasheet PDF文件第1页浏览型号PDU53-1000M的Datasheet PDF文件第2页浏览型号PDU53-1000M的Datasheet PDF文件第3页 
PDU53  
DELAY LINE AUTOMATED TESTING  
TEST CONDITIONS  
INPUT:  
OUTPUT:  
Ambient Temperature: 25oC ± 3oC  
Supply Voltage (Vcc): -4.5V ± 0.1V  
Load:  
50to -2V  
5pf ± 10%  
Cload  
:
Input Pulse:  
Standard 100K ECL  
Threshold: (VOH + VOL) / 2  
levels  
50Max.  
(Rising & Falling)  
Source Impedance:  
Rise/Fall Time:  
1.0 ns Max. (measured  
between 20% and 80%)  
PWIN = 10ns  
Pulse Width:  
Period:  
PERIN = 100ns  
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.  
REF  
PULSE  
OUT  
IN  
OUT  
IN  
DEVICE UNDER  
TEST (DUT)  
OSCILLOSCOPE  
GENERATOR  
TRIG  
TRIG  
ADDRESS SELECT  
Test Setup  
PERIN  
PWIN  
TRISE  
TFALL  
INPUT  
VIH  
80%  
50%  
80%  
50%  
20%  
SIGNAL  
VIL  
20%  
TRISE  
TFALL  
OUTPUT  
SIGNAL  
VOH  
50%  
50%  
VOL  
Timing Diagram For Testing  
Doc #98003  
3/18/98  
DATA DELAY DEVICES, INC.  
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com  
4

与PDU53-1000M相关器件

型号 品牌 获取价格 描述 数据表
PDU-53-1000MC3 DATADELAY

获取价格

ACTIVE DELAY LINE, TRUE OUTPUT, DSO16
PDU53-1000MC3 DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
PDU53-100C3 DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
PDU-53-100M DATADELAY

获取价格

ACTIVE DELAY LINE, TRUE OUTPUT, DIP16, DIP-16
PDU53-100M DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
PDU-53-100MC3 DATADELAY

获取价格

ACTIVE DELAY LINE, TRUE OUTPUT, DSO16
PDU53-100MC3 DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
PDU53-1200 DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
PDU53-1200C3 DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
PDU53-1200M DATADELAY

获取价格

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)