Datasheet > PDM41256LA12TTR

PDM41256LA12TTR

更新时间： 2024-11-18 23:27:07

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
8页	254K
描述
x8 SRAM

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PDM41256LA12TTR 数据手册

PDM41256

256K Static RAM

32K x 8-Bit

Description

Features

The PDM41256 is a high-performance CMOS static

RAM organized as 32,768 x 8 bits. Writing to this

device is accomplished when the write enable (WE)

and the chip enable (CE) inputs are both LOW.

Reading is accomplished when WE remains HIGH

and CE and OE are both LOW.

■ High-speed access times

Com’l: 7, 8, 10, 12 and 15ns

Ind’l: 8, 10, 12 and 15ns

(use 15ns for slower designs)

■ Low power operation (typical)

- PDM41256SA

Active: 475 mW

Standby: 100 mW

- PDM41256LA

Active: 425mW

The PDM41256 operates from a single +5V power

supply and all the inputs and outputs are fully TTL-

compatible. The PDM41256 comes in two versions:

the standard power version PDM41256SA and the

low power version PDM41256LA. Both versions are

functionally the same and differ only in their power

consumption.

Standby: 25 mW

■ Single +5V (±10%) power supply

■ TTL-compatible inputs and outputs

■ Packages

The PDM41256 is available in a 28-pin plastic TSOP

(I) and a 28-pin 300-mil plastic SOJ.

Plastic SOJ (300 mil) - SO

Plastic TSOP (I) - T

Functional Block Diagram

•

Decoder

Memory

•

Addresses

Matrix

•

A ₁₄

• • • • •

I/O₀

Input

Data

Control

Column I/O

•

I/O₇

•

Rev. 4.4 - 4/29/98

12 3 4 5 6 7 8

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