Datasheet > PDI1284P11DGG,698

PDI1284P11DGG,698

更新时间： 2024-11-20 21:11:15

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
16页	89K
描述
PDI1284P11 - 3.3 V parallel interface transceiver/buffer TSSOP 48-Pin

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PDI1284P11DGG,698 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	TSSOP
包装说明：	PLASTIC, TSSOP2-48	针数：	48
Reach Compliance Code：	unknown	风险等级：	5.68
Base Number Matches：	1

PDI1284P11DGG,698 数据手册

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PDI1284P11

3.3 V parallel interface transceiver/buffer

Rev. 03 — 25 August 2008

Product data sheet

1. General description

The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit,

bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19

signal lines deﬁned by the IEEE 1284 interface speciﬁcation for Byte, Nibble, EPP, and

ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to

interface 3.3 V or 5.0 V devices.

The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the

B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR.

The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs,

depending on the state of the high drive enable pin HD. The A-bus has only totem pole

style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at

_CC= 3.3 V.

2. Features

I Asynchronous operation

I 8-bit transceivers

I Six additional buffer/driver lines peripheral to cable

I Five additional control lines from cable

I 5 V tolerant

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I Latch-up current protection exceeds 500 mA per JEDEC Std 19

I Input hysteresis

I Low-noise operation

I IEEE 1284 compliant level 1 and 2

I Overvoltage protection on B/Y side for off-state

I A side 3-state option

I B side active or resistive pull-up option

I Cable side supply voltage for 5 V or 3 V operation

12 3 4 5 6 7...16

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