Datasheet > PD78F0134M1GB(A)-8EU

PD78F0134M1GB(A)-8EU

更新时间： 2022-11-25 14:44:22

品牌	Logo	应用领域
日电电子 - NEC		微控制器
页数	文件大小	规格书
558页	4329K
描述
8-Bit Single-Chip Microcontrollers

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APPENDIX D REVISION HISTORY

D.1 Major Revisions in This Edition

(1/3)

Page

Description

Throughout

Addition of products

µPD78F0134(A1), 78F0138(A1), 780131(A2), 780132(A2), 780133(A2), 780134(A2), 780136(A2),

780138(A2)

Under development → Under mass production

µPD780131, 780132, 780133, 780134, 780136, 780138, 78F0134, 78F0138,

780131(A), 780132(A), 780133(A), 780134(A), 780136(A), 780138(A), 78F0134(A),

78F0138(A), 780131(A1), 780132(A1), 780133(A1), 780134(A1), 780136(A1), 780138(A1)

Modification of names of the following special function registers (SFRs)

• Ports 0 to 7, and 12 to 14 → Port registers 0 to 7, and 12 to 14

p. 27

Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View)

Modification of 1.5 K1 Family Lineup

p. 29

p. 41

Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions

Addition of Table 2-1 Pin I/O Buffer Power Supplies

p. 36

pp. 43, 44

pp. 45, 46

Modification of descriptions in 2.2.12 AVREF, 2.2.15 REGC, and 2.2.20 VPP (flash memory versions only)

Modification of the following contents in Table 2-2 Pin I/O Circuit Types

• Modification of recommended connection when P60 to P63 are not used

• Modification of I/O circuit type of P62 and P63

• Addition of Note to AV^REF

• Modification of recommended connection when V^PPis not used

p. 70

Modification of Figure 3-20 Data to Be Saved to Stack Memory

Modification of Figure 3-21 Data to Be Restored from Stack Memory

Modification of [Description example] in 3.4.4 Short direct addressing

p. 71

p. 84

pp. 87 to 89

Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack

addressing

p. 90

Addition of Table 4-1 Pin I/O Buffer Power Supplies

Modification of Table 4-3 Port Configuration

p. 92

p. 102

p. 110

p. 112

Modification of Figure 4-11 Block Diagram of P20 to P27

Addition of Remark to Figure 4-19 Block Diagram of P130

Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, P12 to P14) to 4.3

Registers Controlling Port Function

p. 116

p. 118

p. 119

p. 124

Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode

Modification of Figure 5-1 Block Diagram of Clock Generator

Addition of Note to 5.3 (1) Processor clock control register (PCC)

Addition of Cautions 2 and 3 to Figure 5-6 Format of Oscillation Stabilization Time Counter Status

pp. 126 to 128

Modification of Figure 5-8 Examples of External Circuit of X1 Oscillator, Figure 5-9 Examples of

External Circuit of Subsystem Clock Oscillator, and Figure 5-10 Examples of Incorrect Resonator

Connection

556

User’s Manual U16228EJ2V0UD

1...553 554 555556557 558

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