Datasheet > PD46184184BF1-E40-EQ1-A

PD46184184BF1-E40-EQ1-A

更新时间： 2024-11-24 12:03:35

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器双倍数据速率
页数	文件大小	规格书
39页	598K
描述
18M-BIT DDR II SRAM 4-WORD BURST OPERATION

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中文翻译

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数据手册

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Datasheet

μPD46185084B

μPD46185094B

μPD46185184B

μPD46185364B

R10DS0113EJ0200

Rev.2.00

18M-BIT QDR^TMII SRAM

4-WORD BURST OPERATION

Nov 09, 2012

Description

The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the

μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous

quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory

cell.

The μPD46185084B, μPD46185094B, μPD46185184B and μPD46185364B integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are

latched on the positive edge of K and K#. These products are suitable for application which require

synchronous operation, high speed, low voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

R10DS0113EJ0200 Rev.2.00

Nov 09, 2012

Page 1 of 38

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中文翻译

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与PD46184184BF1-E40-EQ1-A相关器件

型号	品牌	获取价格	描述	数据表
PD46184184BF1-E40Y-EQ1	RENESAS	获取价格	18M-BIT DDR II SRAM 4-WORD BURST OPERATION
PD46184184BF1-E40Y-EQ1-A	RENESAS	获取价格	18M-BIT DDR II SRAM 4-WORD BURST OPERATION
PD46184185B	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E33-EQ1	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E33-EQ1-A	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E33Y-EQ1	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E33Y-EQ1-A	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E40-EQ1	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E40-EQ1-A	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
PD46184185BF1-E40Y-EQ1	RENESAS	获取价格	18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

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