Datasheet > PD44325094BF5-E40-FQ1

PD44325094BF5-E40-FQ1

更新时间： 2024-11-25 00:38:11

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
40页	458K
描述
36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION

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Datasheet

μPD44325084B

μPD44325094B

μPD44325184B

μPD44325364B

R10DS0039EJ0200

Rev.2.00

September 12, 2011

36M-BIT QDR^TMII SRAM

4-WORD BURST OPERATION

Description

The μPD44325084B is a 4,194,304-word by 8-bit, the μPD44325094B is a 4,194,304-word by 9-bit, the

μPD44325184B is a 2,097,152-word by 18-bit and the μPD44325364B is a 1,048,576-word by 36-bit

synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-

transistor memory cell.

The μPD44325084B, μPD44325094B, μPD44325184B and μPD44325364B integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are

latched on the positive edge of K and K#. These products are suitable for application which require

synchronous operation, high speed, low voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15 x 17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz) , 3.5 ns (287MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

R10DS0039EJ0200 Rev.2.00

September 12, 2011

Page 1 of 39

12 3 4 5 6 7...40

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