Datasheet > PCX7410MGSU500L

PCX7410MGSU500L

更新时间： 2023-01-02 22:17:34

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
51页	926K
描述
RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,

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PCX7410MGSU500L 数据手册

Features

• 22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)

• 917MIPS at 500 MHz

• Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)

• Seven Selectable Core-to-L2 Frequency Divisors

• Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)

• Selectable L2 interface of 1.8V or 2.5V

• P_DTypical 5.3W at 500 MHz, Full Operating Conditions

• Nap, Doze and Sleep Modes for Power Saving

• Superscalar (Four Instructions fetched per Clock Cycle)

• 4 GB Direct Addressing Range

PowerPC 7410

RISC

Microprocessor

Preliminary

Specification

β-site

• Virtual Memory: 4 hexabytes (2⁵²)

• 64-bit Data and 32-bit Address Bus Interface

• 32 KB Instruction and Data Cache

• Eight Independent Execution Units and Three Register Files

• Write-back and Write-through Operations

• f_INTMax = 450 MHz (500 MHz to be confirmed)

• f_BUSMax = 133 MHz

Description

The PC7410 is the second microprocessor that uses the fourth (G4) full implementa-

tion of the PowerPC^™Reduced Instruction Set Computer (RISC) architecture. It is

fully JTAG-compliant.

The PC7410 maintains some of the characteristics of G3 microprocessors:

PC7410

•

The design is superscalar, capable of issuing three instructions per clock cycle

into eight independent execution units

The microprocessor provides four software controllable power-saving modes and

a thermal assist unit management

The microprocessor has separate 32-Kbyte, physically-addressed instruction and

data caches with dedicated L2 cache interface with on-chip L2 tags

In addition, the PC7410 integrates full hardware-based multiprocessing capability,

including a 5-state cache coherency protocol (4 MESI states plus a fifth state for

shared intervention) and an implementation of the new AltiVec^™technology instruc-

tion set.

New features have been developed to make latency equal for double-precision and

single-precision floating-point operations involving multiplication. Additionally, in mem-

ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX

bus interface.

Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache

interface.

Rev. 2141B–HIREL–01/03

12 3 4 5 6 7...51

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