Datasheet > PCX7410MGSU500L

PCX7410MGSU500L

更新时间： 2023-01-02 22:17:34

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
51页	926K
描述
RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,

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中文翻译

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数据手册

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PCX7410MGSU500L 数据手册

–

Supports all PowerPC memory coherency modes

Non-blocking instruction and data cache

Separate copy of data cache tags for efficient snooping

No snooping of instruction cache except for ICBI instruction

•

Level 2 (L2) Cache Interface

–

Internal L2 cache controller and tags; external data SRAMs

512K, 1M and 2-Mbyte 2-way set associative L2 cache support

Copyback or write-through data cache (on a page basis or for all L2)

32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size

Supports pipelined (register-register) synchronous burst SRAMs and

pipelined (register-register) late-write synchronous burst SRAMs

–

Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM

(either all, half or none of L2 SRAM must be configured as direct mapped.

Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4

supported

–

64-bit data bus which also support 32-bits bus mode

Selectable interface voltages of 1.8V and 2.5V

•

Memory Management Unit

–

128 entry, 2-way set associative instruction TLB

128 entry, 2-way set associative data TLB

Hardware reload for TLBs

Four instruction BATs and four data BATs

Virtual memory support for up to four petabytes (2⁵²) of virtual memory

Real memory support for up to four gigabytes (2³²) of physical memory

Snooped and invalidated for TLBI instructions

•

Efficient Data Flow

–

All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are

128 bits wide

–

dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF

L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s

Up to eight outstanding out-of-order cache misses between dL1 and L2/bus

Up to seven outstanding out-of-order transactions on the bus

Load folding to fold new dL1 misses into older outstanding load and store

misses to the same line

–

Store miss merging for multiple store misses to the same line. Only

coherency action taken (i.e., address only) for store misses merged to all 32

bytes of a cache line (no data tenure needed).

–

Two-entry finished store queue and four-entry completed store queue

between load/store unit and dL1

Separate additional queues for efficient buffering of outbound data (castouts,

write throughs, etc.) from dL1 and L2

•

Bus Interface

–

MPX bus extension to 60X processor interface

Mode-compatible with 60x processor interface

32-bit address bus

PC7410

2141B–HIREL–01/03

1...3 4 567 8 9...51

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与PCX7410MGSU500L相关器件

型号	品牌	获取价格	描述	数据表
PCX7410MGSU500LE	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360, COLUMN INTERPOSER, CERAMIC, BGA-360
PCX7410MGSU500N	MICROCHIP	获取价格	RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360
PCX7410MGU400L	MICROCHIP	获取价格	RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360,
PCX7410MGU400LE	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, CERAMIC, BGA-360
PCX7410MGU400N	MICROCHIP	获取价格	RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360
PCX7410MGU400NE	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, CERAMIC, BGA-360
PCX7410MGU450N	MICROCHIP	获取价格	RISC Microprocessor, 32-Bit, 450MHz, CMOS, CBGA360
PCX7410MGU450NE	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 450MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PI
PCX7410MGU500L	MICROCHIP	获取价格	RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360
PCX7410MGU500LE	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360, CERAMIC, BGA-360

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