PC7410FS - Rev.2 – 03/02
PC7410 PowerPC™ Microprocessor
Fact Sheet
The MPC7410 PowerPCTM microprocessor is a high-performance, low-power, 32-bit implementation of the PowerPC
RISC architecture combined with a full 128-bit implementation of Motorola’s AltiVecTM technology. This creates a
microprocessor ideal for leading-edge computing, embedded network control, and signal processing applications. The
MPC7410 offers the high-bandwidth MPX bus with minimized signal setup times and reduced idle cycles to increase
maximum operating frequency to over 100 MHz, in addition to increased address and data bus bandwidth. To maintain
compatibility for existing designs, the MPC7410 also supports the 60x bus protocol. MPC7410 microprocessors offer
single-cycle double precision floating-point performance, full symmetric multi-processing, (SMP) capabilities, and support
for up to 2MB of backside L2 cache. While the MPC7410 is software-compatible with existing PowerPC 603e, 740, and
750 microprocessors, to utilize the full potential of the AltiVec technology changes to existing source code is required.
AltiVec Technology
AltiVec Technology expands the capabilities of PowerPC microprocessors by providing leading-edge, general-purpose
processing performance while concurrently addressing high-bandwidth data processing and algorithmic-intensive
computations in a single-chip solution. AltiVec technology:
• Meets the computational demands of networking infrastructure such as multichannel modems, echo cancellation
equipment, and basestation processing.
• Enables faster, more secure encryption methods optimized for the SIMD processing model
• Provides compelling performance for multimedia-oriented desktop computers, desktop publishing, and digital video
processing.
• Enables real-time processing of the most demanding data streams (MPEG-2 encode, continuous speech recognition, real-
time thigh-resolution 3D graphics, etc…)
PC7410 Main Features
Completion
Unit
Branch
Unit
Dispatch
Unit
Eight independent execution units :
- Two integer units
- Double precision floating-point unit
- Vector permit unit
- Vector arithmetic logic unit
- Load/store unit
- System unit
Floating Point
Integer
AltiVec Unit
Unit
Unit
Integer
Reg File
Floating Point
Reg File
AltiVec Reg File
- Branch processing unit
• Cache and MMU support :
- 32-Kbytes physically -addressed instruction and data caches
- 8 way set-associative
Load/Store Unit
- Dedicated L2 cache interface with on-chip L2 tags
- Separate MMUs for instructions and data
- Virtual memory support up to 4 Petabytes (2)52
- Real memory support up to 4 Gigabytes (2)32
- 128 entry instructions and data TLBs
I MMU
Inst. Cache
D MMU
Data Cache
L2
tags
Bus Interface Unit
64-bit data
60x / MPX Bus
32/64-bit
32-bit address
L2-Cache Port
L2 Data Bus