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PCX7410VGU450N PDF预览

PCX7410VGU450N

更新时间: 2024-02-12 17:59:14
品牌 Logo 应用领域
美国微芯 - MICROCHIP 外围集成电路
页数 文件大小 规格书
51页 926K
描述
RISC Microprocessor, 32-Bit, 450MHz, CMOS, CBGA360

PCX7410VGU450N 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:BGA, BGA360,19X19,50Reach Compliance Code:unknown
风险等级:5.51位大小:32
JESD-30 代码:S-XBGA-B360JESD-609代码:e0
端子数量:360封装主体材料:CERAMIC
封装代码:BGA封装等效代码:BGA360,19X19,50
封装形状:SQUARE封装形式:GRID ARRAY
电源:1.5,1.8/2.5 V认证状态:Not Qualified
速度:450 MHz子类别:Microprocessors
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

PCX7410VGU450N 数据手册

 浏览型号PCX7410VGU450N的Datasheet PDF文件第2页浏览型号PCX7410VGU450N的Datasheet PDF文件第3页浏览型号PCX7410VGU450N的Datasheet PDF文件第4页浏览型号PCX7410VGU450N的Datasheet PDF文件第5页浏览型号PCX7410VGU450N的Datasheet PDF文件第6页浏览型号PCX7410VGU450N的Datasheet PDF文件第7页 
Features  
22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)  
917MIPS at 500 MHz  
Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)  
Seven Selectable Core-to-L2 Frequency Divisors  
Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)  
Selectable L2 interface of 1.8V or 2.5V  
PD Typical 5.3W at 500 MHz, Full Operating Conditions  
Nap, Doze and Sleep Modes for Power Saving  
Superscalar (Four Instructions fetched per Clock Cycle)  
4 GB Direct Addressing Range  
PowerPC 7410  
RISC  
Microprocessor  
Preliminary  
Specification  
β-site  
Virtual Memory: 4 hexabytes (252)  
64-bit Data and 32-bit Address Bus Interface  
32 KB Instruction and Data Cache  
Eight Independent Execution Units and Three Register Files  
Write-back and Write-through Operations  
fINT Max = 450 MHz (500 MHz to be confirmed)  
fBUS Max = 133 MHz  
Description  
The PC7410 is the second microprocessor that uses the fourth (G4) full implementa-  
tion of the PowerPCReduced Instruction Set Computer (RISC) architecture. It is  
fully JTAG-compliant.  
The PC7410 maintains some of the characteristics of G3 microprocessors:  
PC7410  
The design is superscalar, capable of issuing three instructions per clock cycle  
into eight independent execution units  
The microprocessor provides four software controllable power-saving modes and  
a thermal assist unit management  
The microprocessor has separate 32-Kbyte, physically-addressed instruction and  
data caches with dedicated L2 cache interface with on-chip L2 tags  
In addition, the PC7410 integrates full hardware-based multiprocessing capability,  
including a 5-state cache coherency protocol (4 MESI states plus a fifth state for  
shared intervention) and an implementation of the new AltiVectechnology instruc-  
tion set.  
New features have been developed to make latency equal for double-precision and  
single-precision floating-point operations involving multiplication. Additionally, in mem-  
ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX  
bus interface.  
Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache  
interface.  
Rev. 2141B–HIREL–01/03  

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