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PCS3P625Z05B PDF预览

PCS3P625Z05B

更新时间: 2022-12-21 22:58:29
品牌 Logo 应用领域
PULSECORE /
页数 文件大小 规格书
15页 547K
描述
High Frequency Timing-Safe™ Peak EMI reduction IC

PCS3P625Z05B 数据手册

 浏览型号PCS3P625Z05B的Datasheet PDF文件第1页浏览型号PCS3P625Z05B的Datasheet PDF文件第3页浏览型号PCS3P625Z05B的Datasheet PDF文件第4页浏览型号PCS3P625Z05B的Datasheet PDF文件第5页浏览型号PCS3P625Z05B的Datasheet PDF文件第6页浏览型号PCS3P625Z05B的Datasheet PDF文件第7页 
PCS3P625Z05B/C  
PCS3P625Z09B/C  
May 2008  
rev 0.1  
Spread Spectrum Frequency Generation  
The clocks in digital systems are typically square waves  
with a 50% duty cycle and as frequencies increase the  
edge rates also get faster. Analysis shows that a square  
wave is composed of fundamental frequency and  
harmonics. The fundamental frequency and harmonics  
generate the energy peaks that become the source of  
EMI. Regulatory agencies test electronic equipment by  
measuring the amount of peak energy radiated from the  
equipment. In fact, the peak level allowed decreases as  
the frequency increases. The standard methods of  
reducing EMI are to use shielding, filtering, multi-layer  
PCBs etc. These methods are expensive. Spread  
spectrum clocking reduces the peak energy by reducing  
the Q factor of the clock. This is done by slowly  
modulating the clock frequency. The PCS3P625Z05/09  
uses the center modulation spread spectrum technique in  
which the modulated output frequency varies above and  
below the reference frequency with  
a
specified  
modulation rate. With center modulation, the average  
frequency is the same as the unmodulated frequency and  
there is no performance degradation  
Zero Delay and Skew Control  
For applications requiring zero input-output delay, all  
outputs, including DLY_CTRL, must be equally loaded.  
Even if DLY_CTRL is not used, it must have a capacitive  
load equal to that on other outputs, for obtaining zero-  
input-output delay.  
All outputs should be uniformly loaded to achieve Zero  
Delay between input and output. Since the DLY_CTRL pin  
is the internal feedback to the PLL, its relative loading can  
adjust the input-output delay.  
Timing-Safe™ technology  
Timing-Safe™ technology is the ability to modulate a  
clock source with Spread Spectrum technology and  
maintain synchronization with any associated data path.  
High Frequency Timing-Safe™ Peak EMI Reduction IC  
2 of 15  
Notice: The information in this document is subject to change without notice.  

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