5秒后页面跳转
PCS3P622S04JG-08-TR PDF预览

PCS3P622S04JG-08-TR

更新时间: 2024-11-25 05:59:59
品牌 Logo 应用领域
PULSECORE 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
10页 540K
描述
Low Frequency Timing-Safe™ Peak EMI reduction IC

PCS3P622S04JG-08-TR 技术参数

生命周期:Obsolete包装说明:4.40 MM, GREEN, TSSOP-8
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NJESD-30 代码:R-PDSO-G8
长度:4.4 mm端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:20 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH主时钟/晶体标称频率:20 MHz
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

PCS3P622S04JG-08-TR 数据手册

 浏览型号PCS3P622S04JG-08-TR的Datasheet PDF文件第2页浏览型号PCS3P622S04JG-08-TR的Datasheet PDF文件第3页浏览型号PCS3P622S04JG-08-TR的Datasheet PDF文件第4页浏览型号PCS3P622S04JG-08-TR的Datasheet PDF文件第5页浏览型号PCS3P622S04JG-08-TR的Datasheet PDF文件第6页浏览型号PCS3P622S04JG-08-TR的Datasheet PDF文件第7页 
May 2007  
rev 0.3  
PCS3P622S04J  
Low Frequency Timing-Safe™ Peak EMI reduction IC  
General Features  
with Peak EMI Reduction. PCS3P622S04J accepts one  
reference input and drives out four low-skew clocks.  
PCS3P622S04J has an on-chip PLL that locks to an input  
clock on the XIN/CLKIN pin. The PLL feedback is on-chip  
and is obtained from the CLKOUT pad, internal to the  
device. PCS3P622S04J has a crystal oscillator interface.  
An inexpensive crystal will provide the clock source for  
distribution. It is available in 8 pin TSSOP.  
Low Frequency Clock Distribution with Timing-  
Safe™ and Peak EMI Reduction  
Input frequency range: 4MHz - 20MHz  
Zero input - output propagation delay  
Low-skew outputs  
Output-output skew less than 250pS  
Device-device skew less than 700pS  
Less than 200pS Cycle-to-cycle jitter  
3.3V Operation  
Commercial temperature range  
Available in 8pin TSSOP(4.4MM-Body)  
First True Drop-in solution  
All outputs have less than 200pS of Cycle-to-cycle jitter.  
The input and output propagation delay is guaranteed to be  
less than 350pS, and the output-to-output skew is  
guaranteed to be less than 250pS.  
Refer Spread Spectrum Control and Input-Output Skew  
Table” for values of deviation and Input-Output Skew  
Product Description  
PCS3P622S04J is a versatile, 3.3V Zero-delay buffer  
designed to distribute low frequency Timing-Safe™ clocks  
Block Diagram  
VDD  
CLK1  
CLKIN / XIN  
XOUT  
CLK2  
Crystal  
PLL  
Oscillator  
CLK3  
CLKOUT  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

与PCS3P622S04JG-08-TR相关器件

型号 品牌 获取价格 描述 数据表
PCS3P622S04JG-08-TT PULSECORE

获取价格

Low Frequency Timing-Safe™ Peak EMI reduction
PCS3P622Z05B PULSECORE

获取价格

Low Frequency Timing-Safe™ Peak EMI reduction
PCS3P622Z05BG-08-ST ONSEMI

获取价格

PLL BASED CLOCK DRIVER
PCS3P622Z05BG-16-ST ONSEMI

获取价格

IC PLL BASED CLOCK DRIVER, Clock Driver
PCS3P622Z05BG-16-TR ONSEMI

获取价格

IC PLL BASED CLOCK DRIVER, Clock Driver
PCS3P622Z05BG-16-TT ONSEMI

获取价格

IC PLL BASED CLOCK DRIVER, Clock Driver
PCS3P622Z05C PULSECORE

获取价格

Low Frequency Timing-Safe™ Peak EMI reduction
PCS3P622Z05CG-08-SR ONSEMI

获取价格

PLL BASED CLOCK DRIVER
PCS3P622Z05CG-08-ST ONSEMI

获取价格

PLL BASED CLOCK DRIVER
PCS3P622Z05CG-08-TR ONSEMI

获取价格

IC PLL BASED CLOCK DRIVER, Clock Driver