Datasheet > PCS2P3805E

PCS2P3805E

更新时间： 2024-09-29 05:59:55

品牌	Logo	应用领域
PULSECORE		时钟驱动器
页数	文件大小	规格书
11页	193K
描述
3.3V CMOS Dual 1-To-5 Clock Driver

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数据手册

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PCS2P3805E 数据手册

September 2006

rev 0.3

PCS2P3805E

3.3V CMOS Dual 1-To-5 Clock Driver

Functional Description

Features

•

Advanced CMOS Technology

The PCS2P3805E is a 3.3V clock driver built using

advanced CMOS technology. The device consists of two

banks of drivers, each with a 1:5 fanout and its own output

enable control. The device has a "heartbeat" monitor for

diagnostics and PLL driving. The MON output is identical to

all other outputs and complies with the output specifications

in this document. The PCS2P3805E offers low capacitance

inputs. The PCS2P3805E is designed for high speed clock

distribution where signal quality and skew are critical. The

PCS2P3805E also allows single point-to-point transmission

line driving in applications such as address distribution,

where one signal must be distributed to multiple receivers

with low skew and high signal quality.

Guaranteed low skew < 200pS (max)

Very low propagation delay < 2.5nS (max)

Very low duty cycle distortion < 270pS (max)

Very low CMOS power levels

Operating frequency up to 166MHz

TTL compatible inputs and outputs

Inputs can be driven from 3.3V or 5V components

Two independent output banks with 3-state control

1:5 fanout per bank

"Heartbeat" monitor output

V_CC= 3.3V ± 0.3V

Available in SSOP and QSOP Packages

Block Diagram

Pin Diagram

V_CCA

OA₁

V_CCB

OE_A

IN_A

OB₁

OB₂

OB₃

OA₁– OA₅

OA₂

OA₃

GND_A

GND_B

OB₄

PCS2P3805E

IN_B

OB₁– OB₅

MON

OA₄

OA₅

OB₅

OE_B

GND_Q

MON

OE_B

OE_A

IN_A

IN_B

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

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