Datasheet > PCS2P5T9050A

PCS2P5T9050A

更新时间： 2024-01-24 23:06:45

品牌	Logo	应用领域
PULSECORE		时钟
页数	文件大小	规格书
10页	430K
描述
2.5V Single Data Rate1:5 Clock Buffer Terabuffer

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数据手册

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PCS2P5T9050A 数据手册

November 2006

rev 0.2

PCS2P5T9050A

2.5V Single Data Rate1:5 Clock Buffer Terabuffer

Features

The PCS2P5T9050A 2.5V single data rate (SDR) clock

buffer is a single-ended input to five single-ended outputs

buffer built on advanced metal CMOS technology. The

SDR clock buffer fan-out from a single input to five

single-ended outputs reduces the loading on the preceding

driver and provides an efficient clock distribution network.

Multiple power and grounds reduce noise.

•

Optimized for 2.5V LVTTL

Guaranteed Low Skew < 25pS (max)

Very low duty cycle distortion< 300pS (max)

High speed propagation delay < 1.8nS. (max)

Up to 200MHz operation

Very low CMOS power levels

Hot Insert able and over-voltage tolerant inputs

1:5 fan-out buffer

Applications:

2.5V Supply Voltage

Available in TSSOP Package

PCS2P5T9050A is targeted towards Clock and signal

distribution applications.

Functional Description

Block Diagram

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

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