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PCA9534PW/DG,118

更新时间： 2024-02-14 20:05:58
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
27页 262K
描述
PCA9534 - 8-bit I2C-bus and SMBus low power I/O port with interrupt TSSOP 16-Pin

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PCA9534PW/DG,118 技术参数

Source Url Status Check Date：2013-06-14 00:00:00生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP,
针数：16Reach Compliance Code：unknown
风险等级：5.78JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
I/O 线路数量：8端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH座面最大高度：1.1 mm
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

PCA9534PW/DG,118 数据手册

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PCA9534  
NXP Semiconductors  
8-bit I2C-bus and SMBus low power I/O port with interrupt  
Table 5.  
Register 0 - Input Port register bit description  
Bit  
7
Symbol  
Access  
Value  
Description  
I7  
I6  
I5  
I4  
I3  
I2  
I1  
I0  
read only  
read only  
read only  
read only  
read only  
read only  
read only  
read only  
X
X
X
X
X
X
X
X
determined by externally applied logic level  
6
5
4
3
2
1
0
6.1.3 Register 1 - Output Port register  
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.  
Bit values in this register have no effect on pins defined as inputs. Reads from this register  
return the value that is in the flip-flop controlling the output selection, not the actual pin  
value.  
Table 6.  
Register 1 - Output Port register bit description  
Legend: * default value.  
Bit  
7
Symbol  
O7  
Access  
Value  
1*  
Description  
R
R
R
R
R
R
R
R
reflects outgoing logic levels of pins defined as  
outputs by Register 3  
6
O6  
1*  
5
O5  
1*  
4
O4  
1*  
3
O3  
1*  
2
O2  
1*  
1
O1  
1*  
0
O0  
1*  
6.1.4 Register 2 - Polarity Inversion register  
This register allows the user to invert the polarity of the Input Port register data. If a bit in  
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in  
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.  
Table 7.  
Register 2 - Polarity Inversion register bit description  
Legend: * default value.  
Bit  
7
Symbol  
N7  
Access  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Value  
0*  
Description  
inverts polarity of Input Port register data  
0 = Input Port register data retained (default value)  
1 = Input Port register data inverted  
6
N6  
0*  
5
N5  
0*  
4
N4  
0*  
3
N3  
0*  
2
N2  
0*  
1
N1  
0*  
0
N0  
0*  
PCA9534  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2017. All rights reserved.  
Product data sheet  
Rev. 4 — 7 November 2017  
6 of 27  
 
 
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