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PCA9534ARGTR PDF预览

PCA9534ARGTR

更新时间： 2024-02-22 00:11:41
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路输出元件PC时钟
页数 文件大小 规格书
35页 644K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

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PCA9534ARGTR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：QFN-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.82Is Samacsys：N
最大时钟频率：0.4 MHzJESD-30 代码：S-PQCC-N16
JESD-609代码：e4长度：4 mm
湿度敏感等级：2位数：8
I/O 线路数量：8端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC16,.16SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：2.5/5 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Parallel IO Ports最大压摆率：0.175 mA
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9534ARGTR 数据手册

 浏览型号PCA9534ARGTR的Datasheet PDF文件第6页浏览型号PCA9534ARGTR的Datasheet PDF文件第7页浏览型号PCA9534ARGTR的Datasheet PDF文件第8页浏览型号PCA9534ARGTR的Datasheet PDF文件第10页浏览型号PCA9534ARGTR的Datasheet PDF文件第11页浏览型号PCA9534ARGTR的Datasheet PDF文件第12页 
PCA9534A  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS141B–SEPTEMBER 2006–REVISED MARCH 2007  
Reads  
The bus master first must send the PCA9534A address with the least-significant bit set to a logic 0 (see Figure 4  
for device address). The command byte is sent after the address and determines which register is accessed.  
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data  
from the register defined by the command byte then is sent by the PCA9534A (see Figure 8 and Figure 9). After  
a restart, the value of the register defined by the command byte matches the register being accessed when the  
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no  
limitation on the number of data bytes received in one read transmission, but when the final byte is received, the  
bus master must not acknowledge the data.  
ACK From  
Master  
ACK From  
Slave  
ACK From  
Slave  
ACK From  
Slave  
Data from Register  
Data  
Slave Address  
Slave Address  
Command Byte  
A
S
A
0
1
1
1 A2 A1 A0  
1
A
S
0
1
1
1
A2 A1 A0  
0
A
R/W  
R/W  
NACK From  
Master  
Data from Register  
Data  
P
NA  
Last Byte  
Figure 8. Read From Register  
<br/>  
1
2
3
4
5
6
7
8
9
SCL  
SDA  
Data From Port  
Data 1  
Slave Address  
Data From Port  
Data 4  
S
0
1
1
1
A2 A1 A0  
R/W  
0
A
P
A
NA  
Start  
Condition  
NACK From  
ACK From  
Slave  
ACK From  
Master  
Stop  
Condition  
Master  
Read From  
Port  
Data Into  
Port  
Data 2  
Data 5  
Data 3  
Data 4  
t
ph  
t
ps  
INT  
t
iv  
t
ir  
A. This figure assumes that the command byte has previously been programmed with 00h.  
B. Transfer of data can be stopped at any moment by a stop condition.  
C. This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address  
call and the actual data transfer from the P Port. See Figure 8 for these details.  
Figure 9. Read Input Port Register  
9
Submit Documentation Feedback  
 
 
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