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PCA9534ARGTR PDF预览

PCA9534ARGTR

更新时间: 2024-01-27 01:51:19
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路输出元件PC时钟
页数 文件大小 规格书
35页 644K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

PCA9534ARGTR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.82Is Samacsys:N
最大时钟频率:0.4 MHzJESD-30 代码:S-PQCC-N16
JESD-609代码:e4长度:4 mm
湿度敏感等级:2位数:8
I/O 线路数量:8端口数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC16,.16SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5/5 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Parallel IO Ports最大压摆率:0.175 mA
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9534ARGTR 数据手册

 浏览型号PCA9534ARGTR的Datasheet PDF文件第3页浏览型号PCA9534ARGTR的Datasheet PDF文件第4页浏览型号PCA9534ARGTR的Datasheet PDF文件第5页浏览型号PCA9534ARGTR的Datasheet PDF文件第7页浏览型号PCA9534ARGTR的Datasheet PDF文件第8页浏览型号PCA9534ARGTR的Datasheet PDF文件第9页 
PCA9534A  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS141BSEPTEMBER 2006REVISED MARCH 2007  
Interface Definition  
BIT  
BYTE  
7 (MSB)  
6
H
5
H
4
H
3
2
1
0 (LSB)  
R/W  
I2C slave address  
Px I/O data bus  
L
A2  
P3  
A1  
P2  
A0  
P1  
P7  
P6  
P5  
P4  
P0  
Device Address  
Figure 4 shows the address byte of the PCA9534A.  
Slave Address  
0
1
1
1
A2 A1 A0 R/W  
Hardware  
Selectable  
Fixed  
Figure 4. PCA9534A Address  
Address Reference  
INPUTS  
I2C BUS SLAVE ADDRESS  
A2  
L
A1  
L
A0  
L
56 (decimal), 38 (hexadecimal)  
57 (decimal), 39 (hexadecimal)  
58 (decimal), 3A (hexadecimal)  
59 (decimal), 3B (hexadecimal)  
60 (decimal), 3C (hexadecimal)  
61 (decimal), 3D (hexadecimal)  
62 (decimal), 3E (hexadecimal)  
63 (decimal), 3F (hexadecimal)  
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read  
is selected, while a low (0) selects a write operation.  
Control Register and Command Byte  
Following the successful acknowledgment of the address byte, the bus master sends a command byte which is  
stored in the control register in the PCA9534A. Two bits of this command byte state the operation (read or write)  
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can  
be written or read through the I2C bus. The command byte is sent only during a write transmission.  
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until  
a new command byte has been sent.  
0
0
0
0
0
0
B1 B0  
Figure 5. Control Register Bits  
6
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