Datasheet > PCA0300A-LF_10

PCA0300A-LF_10

更新时间： 2024-02-22 05:33:47

品牌	Logo	应用领域
ZCOMM		/
页数	文件大小	规格书
2页	164K
描述
PHASE LOCKED LOOP

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中文翻译

获取价格

数据手册

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PCA0300A-LF_10 数据手册

PCA0300A-LF

PHASE LOCKED LOOP

14118 Stowe Drive, Suite B | Poway, CA 92064

TEL: (858) 621-2700 | FAX: (858) 486-1927

Rev A1

PHASE NOISE (1 Hz BW, typical)

FEATURES

• Frequency Range:

• Step Size:

275 -

100

325 MHz

KHz

•

- Style Package

CPLL

APPLICATIONS

• Satellite Modems

• Mobile Radios

CATV

•

VALUE

275 - 325

UNITS

MHz

PERFORMANCE SPECIFICATIONS

Frequency Range

-97

dBc/Hz

dBc

Phase Noise @ 10 kHz offset (1 Hz BW, typ.)

Harmonic Suppression (2nd, typ.)

Sideband Spurs (typ.)

-7

-65

dBc

Power Output

4±3

dBm

Load Impedance

Step Size

100

2500

kHz

Charge Pump Output Current

Switching Speed (typ., adjacent channel)

Startup Lock Time (typ.)

mSec

°C

-40 to 85

Operating Temperature Range

Package Style

CPLL

POWER SUPPLY REQUIREMENTS

Supply Voltage (Vcc, nom.)

Vdc

Supply Current (Icc, typ.)

All specifications are typical unless otherwise noted and subject to change without notice.

APPLICATION NOTES

• AN-107 : How to Solder Z-COMM VCOs / PLLs

• AN-202 : PLL Functional Description

NOTES:

Reference Oscillator Signal: 5 MHz<

<100 MHz

Frequency Synthesizer IC: Analog Devices - ADF4113

Page 1

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