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PAM1806BZCE3

更新时间： 2024-02-04 04:22:55

品牌	Logo	应用领域
德州仪器 - TI		微控制器和处理器外围集成电路 uCs集成电路 uPs集成电路微处理器
页数	文件大小	规格书
241页	1437K
描述
AM1806 ARM Microprocessor

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PAM1806BZCE3 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	GREEN, PLASTIC, NFBGA-361	针数：	361
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.84	Is Samacsys：	N
其他特性：	IT ALSO OPERATES IN 0.95V MINIMUM SUPPLY	JESD-30 代码：	S-PBGA-B361
长度：	13 mm	端子数量：	361
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.3 mm
最大供电电压：	1.35 V	最小供电电压：	1.25 V
标称供电电压：	1.3 V	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子节距：	0.65 mm	端子位置：	BOTTOM
宽度：	13 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

PAM1806BZCE3 数据手册

AM1806

SPRS658B–FEBRUARY 2010–REVISED MAY 2010

www.ti.com

1.3 Description

The device is a Low-power applications processor based on ARM926EJ-S™.

The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, and high processing performance life through the maximum

flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and

processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and

memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory

Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and

16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core

also has a 8KB RAM (Vector Table) and 64KB ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C) Bus interfaces;

one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel

buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit

general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port

interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable

interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with

RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit

enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary

pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM

external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile

DDR controller.

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters,

FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on

each of two channels. Single-date rate and double-data rate transfers are supported as well as START,

ENABLE and WAIT signals to provide control for a variety of data converters.

A Video Port Interface (VPIF) is included providing a flexible video input/output port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM . These include C compilers, and

scheduling, and a Windows™ debugger interface for visibility into source code execution.

AM1806 ARM Microprocessor

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