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PALC22V10D-10PC PDF预览

PALC22V10D-10PC

更新时间： 2024-02-24 17:40:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 闪存可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
12页 328K
描述
Flash Erasable, Reprogrammable CMOS PAL㈢ Device

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PALC22V10D-10PC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP24,.3
针数：24Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.67
其他特性：10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS架构：PAL-TYPE
最大时钟频率：76.9 MHzJESD-30 代码：R-PDIP-T24
JESD-609代码：e0专用输入次数：11
I/O 线路数量：10输入次数：22
输出次数：10产品条款数：132
端子数量：24最高工作温度：75 °C
最低工作温度：组织：11 DEDICATED INPUTS, 10 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
可编程逻辑类型：FLASH PLD传播延迟：10 ns
认证状态：Not Qualified子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

PALC22V10D-10PC 数据手册

 浏览型号PALC22V10D-10PC的Datasheet PDF文件第3页浏览型号PALC22V10D-10PC的Datasheet PDF文件第4页浏览型号PALC22V10D-10PC的Datasheet PDF文件第5页浏览型号PALC22V10D-10PC的Datasheet PDF文件第7页浏览型号PALC22V10D-10PC的Datasheet PDF文件第8页浏览型号PALC22V10D-10PC的Datasheet PDF文件第9页 
PALC22V10D  
Commercial Switching Characteristics PALC22V10D[2, 7]  
22V10D-7  
Min. Max.  
7.5  
22V10D-10  
22V10D-15  
22V10D-25  
Parameter  
Description  
Input to Output  
Propagation Delay  
Input to Output Enable Delay  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
t
3
3
10  
3
15  
3
25  
ns  
PD  
[8, 9]  
[10]  
[11]  
t
t
t
t
t
t
t
t
t
f
8
8
5
10  
10  
7
15  
15  
8
25  
25  
15  
ns  
ns  
EA  
ER  
CO  
S1  
Input to Output Disable Delay  
[8, 9]  
Clock to Output Delay  
2
5
2
6
2
10  
10  
0
2
15  
15  
0
ns  
Input or Feedback Set-Up Time  
Synchronous Preset Set-Up Time  
Input Hold Time  
ns  
6
7
ns  
S2  
0
0
ns  
H
External Clock Period (t + t )  
10  
3
12  
3
20  
6
30  
13  
13  
33.3  
ns  
P
CO  
S
[6]  
Clock Width HIGH  
ns  
WH  
WL  
MAX1  
[6]  
Clock Width LOW  
External Maximum Frequency  
3
3
6
ns  
100  
76.9  
55.5  
MHz  
[12]  
(1/(t + t ))  
CO  
S
f
f
t
Data Path Maximum Frequency  
166  
133  
142  
111  
83.3  
68.9  
35.7  
38.5  
MHz  
MHz  
ns  
MAX2  
MAX3  
CF  
[6, 13]  
(1/(t  
+ t ))  
WH  
WL  
Internal Feedback Maximum  
[6,14]  
Frequency (1/(t + t ))  
CF  
S
Register Clock to  
2.5  
12  
3
4.5  
20  
13  
25  
[6, 15]  
Feedback Input  
t
t
Asynchronous Reset Width  
8
5
10  
6
15  
10  
25  
25  
ns  
ns  
AW  
Asynchronous Reset Recovery  
Time  
AR  
t
t
t
Asynchronous Reset to  
Registered Output Delay  
13  
ns  
ns  
µs  
AP  
Synchronous Preset Recovery  
Time  
6
1
8
1
10  
1
15  
1
SPR  
[6,16]  
Power-Up Reset Time  
PR  
Notes:  
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test  
Loads and Waveforms is used for tEA(+)  
.
8. Min. times are tested initially and after any design or process changes that may affect these parameters.  
9. This specification is guaranteed for all device outputs changing state in a given access cycle.  
10. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring  
tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.  
11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to  
the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC  
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.  
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.  
13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.  
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.  
15. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS.  
16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a  
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure  
proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.  
6
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