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PAL16R8-7PC PDF预览

PAL16R8-7PC

更新时间： 2024-11-04 04:54:23
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超微 - AMD 可编程逻辑光电二极管输入元件时钟
页数 文件大小 规格书
33页 218K
描述
20-Pin TTL Programmable Array Logic

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中文翻译

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PAL16R8-7PC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, DIP-20
针数：20Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.12
Is Samacsys：N其他特性：POWER-UP RESET; REGISTER PRELOAD; 1 EXTERNAL CLOCK
架构：PAL-TYPE最大时钟频率：74 MHz
JESD-30 代码：R-PDIP-T20JESD-609代码：e0
长度：26.035 mm专用输入次数：8
I/O 线路数量：输入次数：8
输出次数：8产品条款数：64
端子数量：20最高工作温度：75 °C
最低工作温度：组织：8 DEDICATED INPUTS, 0 I/O
输出函数：REGISTERED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
可编程逻辑类型：OT PLD传播延迟：8 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

PAL16R8-7PC 数据手册

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FINAL  
COM’L: -4/5/7/B/B-2/A, D/2  
Advanced  
Micro  
PAL16R8 Family  
20-Pin TTL Programmable Array Logic  
Devices  
DISTINCTIVE CHARACTERISTICS  
■ As fast as 4.5 ns maximum propagation delay  
■ Power-up reset for initialization  
■ Popular 20-pin architectures: 16L8, 16R8, 16R6,  
■ Extensive third-party software and programmer  
16R4  
support through FusionPLD partners  
■ Programmable replacement for high-speed TTL  
■ 20-Pin DIP and PLCC packages save space  
logic  
■ 28-Pin PLCC-4 package provides ultra-clean  
■ Register preload for testability  
high-speed signals  
GENERAL DESCRIPTION  
The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6,  
PAL16R4) includes the PAL16R8-5/4 Series which pro-  
vides the highest speed in the 20-pin TTL PAL device  
family, making the series ideal for high-performance ap-  
plications. The PAL16R8 Family is provided with stan-  
dard 20-pin DIP and PLCC pinouts and a 28-pin PLCC  
pinout. The 28-pin PLCC pinout contains seven extra  
ground pins interleaved between the outputs to reduce  
noise and increase speed.  
The AND array is programmed to create custom product  
terms, while the OR array sums selected terms at the  
outputs.  
In addition, the PAL device provides the following  
options:  
— Variable input/output pin ratio  
— Programmable three-state outputs  
— Registers with feedback  
The devices provide user-programmable logic for re-  
placing conventional SSI/MSI gates and flip-flops at a  
reduced chip count.  
Product terms with all connections opened assume the  
logicalHIGHstate;producttermsconnectedtobothtrue  
and complement of any single input assume the logical  
LOW state. Registers consist of D-type flip-flops that are  
loaded on the LOW-to-HIGH transition of the clock. Un-  
used input pins should be tied to VCC or GND.  
The family allows the systems engineer to implement  
the design on-chip, by opening fuse links to configure  
AND and OR gates within the device, according to the  
desired logic function. Complex interconnections be-  
tween gates, which previously required time-consuming  
layout, are lifted from the PC board and placed on sili-  
con, where they can be easily modified during proto-  
typing or production.  
The entire PAL device family is supported by the  
FusionPLD partners. The PAL family is programmed on  
conventionalPALdeviceprogrammerswithappropriate  
personality and socket adapter modules. Once the PAL  
device is programmed and verified, an additional con-  
nection may be opened to prevent pattern readout. This  
feature secures proprietary circuits.  
The PAL device implements the familiar Boolean logic  
transfer function, the sum of products. The PAL device  
is a programmable AND array driving a fixed OR array.  
PRODUCT SELECTOR GUIDE  
Dedicated  
Product Terms/  
Device  
Inputs  
Outputs  
Output  
Feedback  
Enable  
PAL16L8  
10  
6 comb.  
2 comb.  
7
7
I/O  
–
prog.  
prog.  
PAL16R8  
PAL16R6  
8
8
8 reg.  
8
reg.  
pin  
6 reg.  
2 comb.  
8
7
reg.  
I/O  
pin  
prog.  
PAL16R4  
8
4 reg.  
4 comb.  
8
7
reg.  
I/O  
pin  
prog.  
Publication# 16492 Rev. D Amendment/0  
Issue Date: February 1996  
2-3  
1234567...33

中文翻译

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