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PAC330/150TFQ/T PDF预览

PAC330/150TFQ/T

更新时间: 2024-11-15 19:34:31
品牌 Logo 应用领域
CALMIRCO 光电二极管接口集成电路
页数 文件大小 规格书
3页 123K
描述
Terminator, 8-Line, 33ohm, PDSO24, QSOP-24

PAC330/150TFQ/T 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP,针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
差分输出:NO接口集成电路类型:OTHER TERMINATOR
JESD-30 代码:R-PDSO-G24长度:8.65 mm
功能数量:1信号线数量:8
端子数量:24最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH标称上拉电阻:33 Ω
认证状态:Not Qualified座面最大高度:1.75 mm
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:3.9116 mm
Base Number Matches:1

PAC330/150TFQ/T 数据手册

 浏览型号PAC330/150TFQ/T的Datasheet PDF文件第2页浏览型号PAC330/150TFQ/T的Datasheet PDF文件第3页 
CALIFORNIA MICRO DEVICES  
PACTFSERIES  
®
P/ACTIVE CLOCK TERMINATION AND FILTER  
Features  
Pin Assignments  
• 8 Channels in Miniature QSOP Package  
• Frequency Response to greater than 3 GHz  
• Low In-Band Insertion Loss Maintains  
Signal Integrity  
• Low Distortion, Low Cross Talk  
• ESD Protected  
Applications  
• High speed microprocessor clock termination  
Product Description  
High speed microprocessor systems require well controlled, precise, fast edge-rate clock signals. Clock lines behave as  
transmission lines for fast-edge signals and therefore the lines may exhibit transients caused by reflections and switching  
noise. The PACTF clock filter reduces reflections and slows down edges to help reduce EMI/RFI radiation.  
California Micro Devices’ P/Active Tapped Filter is an integrated thin film resistor-capacitor network designed to filter clock  
lines and suppress EMI/RFI noise in personal computers and peripherals, workstations, Local Area Network (LAN), Asynchro-  
nous Transfer Mode (ATM), and Wide Area Network (WAN). The filter includes ESD protection circuitry which prevents  
device destruction when subjected to ESD discharges less than 2KV. The ESD protection circuitry permits the filter to  
operate on bipolar signals of up to ±6V. California Micro Devices’ PAC TF is housed in a surface mount package suitable  
for bottom side mounting to the board. This integrated network solution minimizes space and routing problems and  
improves reliability and yields.  
SCHEMATIC CONFIGURATION  
S TA N D A R D S P E C IF IC A TIO N S  
Absolute Tolerance (R)  
± 10%  
Absolute Tolerance (C)  
Operating Temperature Range  
Power Rating/Resistor  
Leakage Current  
± 20%  
0°C to 70°C  
100mW  
24 23 22 21 20 19 18 17 16 15 14 13  
1 µA @ 25ºC max.  
< 5% (typical)  
Crosstalk (see Text Circuit)  
ESD Clamp  
Positive Clamp  
Negative Clamp  
ESD Protection*  
> 6 Volts  
< -6 Volts  
2KV min.  
1
2
3
4
5
6
7
8
9
10 11 12  
Storage Temperature  
Package Power Rating  
-60°C to 150°C  
1.00W, max.  
* ESD Protection level guaranteed by design.  
C0380798  
© 2000 California Micro Devices Corp. All rights reserved.  
4/00  
215 Topaz Street, Milpitas, California 95035  
Tel: (408) 263-3214  
Fax: (408) 263-7846  
www.calmicro.com  
1

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