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P89LPC9402FBD PDF预览

P89LPC9402FBD

更新时间: 2024-02-15 04:17:36
品牌 Logo 应用领域
恩智浦 - NXP 驱动器闪存微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
60页 296K
描述
8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 32 segment 4 LCD driver

P89LPC9402FBD 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT791-1, QFP-64针数:64
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.84Is Samacsys:N
具有ADC:NO地址总线宽度:
位大小:8最大时钟频率:18 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:14 mm
湿度敏感等级:2I/O 线路数量:23
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
ROM可编程性:FLASH座面最大高度:1.6 mm
速度:18 MHz最大供电电压:3.6 V
最小供电电压:2.4 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:14 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

P89LPC9402FBD 数据手册

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P89LPC9402  
NXP Semiconductors  
8-bit microcontroller with accelerated two-clock 80C51 core  
I Serial flash In-Circuit Programming (ICP) allows simple production coding with  
commercial EPROM programmers. Flash security bits prevent reading of sensitive  
application programs.  
I Serial flash In-System Programming (ISP) allows coding while the device is mounted  
in the end application.  
I In-Application Programming (IAP) of the flash code memory. This allows changing the  
code in a running application.  
I Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %,  
requiring no external components. The watchdog prescaler is selectable from  
eight values.  
I High-accuracy internal RC oscillator option, with clock doubler option, allows operation  
without external oscillator components. The RC oscillator option is selectable and fine  
tunable.  
I Switching on the fly among internal RC oscillator, watchdog oscillator, external clock  
source provides optimal support of minimal power active mode with fast switching to  
maximum performance.  
I Idle and two different power-down reduced power modes. Improved wake-up from  
Power-down mode (a LOW interrupt input starts execution). Typical power-down  
current is 1 µA (total power-down with voltage comparators disabled).  
I Active-LOW reset. On-chip power-on reset allows operation without external reset  
components. A software reset function is also available.  
I Configurable on-chip oscillator with frequency range options selected by user  
programmed flash configuration bits. Oscillator options support frequencies from  
20 kHz to the maximum operating frequency of 18 MHz.  
I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator  
allowing it to perform an oscillator fail detect function.  
I Programmable port output configuration options: quasi-bidirectional, open-drain,  
push-pull, input-only.  
I High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,  
P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is  
specified for the entire chip.  
I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of  
the pins match or do not match a programmable pattern.  
I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns  
minimum ramp times.  
I Only power and ground connections are required to operate the P89LPC9402 when  
internal reset option is selected.  
I Four interrupt priority levels.  
I Eight keypad interrupt inputs, plus two additional external interrupt inputs.  
I Schmitt trigger port inputs.  
I Second data pointer.  
I Emulation support.  
I LED drive capability (20 mA) on all port pins. A maximum limit is specified for the  
entire chip.  
P89LPC9402_1  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 01 — 22 April 2009  
2 of 60  

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