Datasheet > P89LPC9402FBD,557

P89LPC9402FBD,557

更新时间： 2024-02-18 01:10:32

品牌	Logo	应用领域
恩智浦 - NXP		PC
页数	文件大小	规格书
60页	273K
描述
P89LPC9402 - 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 32 segment 4 LCD driver QFP 64-Pin

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技术参数
数据手册

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P89LPC9402FBD,557 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT791-1, QFP-64	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.82
Base Number Matches：	1

P89LPC9402FBD,557 数据手册

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P89LPC9402

8-bit microcontroller with accelerated two-clock 80C51 core

8 kB 3 V byte-erasable ﬂash with 32 segment 4 LCD driver

Rev. 01 — 22 April 2009

Product data sheet

1. General description

The P89LPC9402 is a multi-chip module consisting of a P89LPC931A1 single-chip

microcontroller combined with a PCF8576D universal LCD driver in a low-cost 64-pin

package. The LCD driver provides 32 segments and supports from 1 to 4 backplanes.

Display overhead is minimized by an on-chip display RAM with auto-increment

addressing.

2. Features

2.1 Principal features

I 8 kB byte-erasable ﬂash code memory organized into 1 kB sectors and 64-byte pages.

Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

I 256-byte RAM data memory.

I 32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes.

I Two analog comparators with selectable inputs and reference source.

I Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer

overﬂow or to become a PWM output).

I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit

prescaler and a programmable and readable 16-bit timer.

I Enhanced UART with a fractional baud rate generator, break detect, framing error

detection, and automatic address detection; 400 kHz byte-wide I²C-bus

communication port and SPI communication port.

I 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

I Enhanced low voltage (brownout) detect allows a graceful system shutdown when

power fails.

I 64-pin LQFP package with 20 microcontroller I/O pins minimum and up to 23

microcontroller I/O pins while using on-chip oscillator and reset options.

2.2 Additional features

I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequency. A

lower clock frequency for the same performance results in power savings and reduced

EMI.

12 3 4 5 6 7...60

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