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P8242AH PDF预览

P8242AH

更新时间: 2024-11-20 03:43:39
品牌 Logo 应用领域
英特尔 - INTEL 微控制器
页数 文件大小 规格书
20页 274K
描述
UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER

P8242AH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP40,.6
针数:40Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.87
具有ADC:NO地址总线宽度:
位大小:8CPU系列:8048
最大时钟频率:12.5 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:R-PDIP-T40JESD-609代码:e0
长度:52.26 mmI/O 线路数量:16
端子数量:40最高工作温度:70 °C
最低工作温度:PWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP40,.6封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
认证状态:Not QualifiedRAM(字节):256
ROM(单词):2048ROM可编程性:MROM
座面最大高度:5.08 mm速度:12.5 MHz
子类别:Microcontrollers最大压摆率:135 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:15.24 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

P8242AH 数据手册

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UPI-41AH/42AH  
UNIVERSAL PERIPHERAL INTERFACE  
8-BIT SLAVE MICROCONTROLLER  
Y
Y
Y
UPI-41: 6 MHz; UPI-42: 12.5 MHz  
Fully Compatible with all Intel and Most  
Other Microprocessor Families  
Pin, Software and Architecturally  
Compatible with all UPI-41 and UPI-42  
Products  
Y
Interchangeable ROM and OTP EPROM  
Versions  
Y
Y
Y
Y
Y
Y
8-Bit CPU plus ROM/OTP EPROM, RAM,  
I/O, Timer/Counter and Clock in a  
Single Package  
Expandable I/O  
Sync Mode Available  
Over 90 Instructions: 70% Single Byte  
2048 x 8 ROM/OTP, 256 x 8 RAM on  
UPI-42, 1024 x 8 ROM/OTP, 128 x 8  
RAM on UPI-41, 8-Bit Timer/Counter, 18  
Programmable I/O Pins  
Available in EXPRESS  
Ð Standard Temperature Range  
Y
Y
int ligent Programming Algorithm  
e
Ð Fast OTP Programming  
Y
Y
One 8-Bit Status and Two Data  
Registers for Asynchronous Slave-to-  
Master Interface  
Available in 40-Lead Plastic and 44-  
Lead Plastic Leaded Chip Carrier  
Packages  
Ý
(See Packaging Spec., Order 240800-001)  
Package Type P and N  
DMA, Interrupt, or Polled Operation  
Supported  
The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer  
to develop customized solutions for peripheral device control.  
They are essentially ‘‘slave’’ microcontrollers, or microcontrollers with a slave interface included on the chip.  
Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS  
Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems.  
To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM  
(OTP). All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to  
production level designs.  
210393–2  
Figure 1. DIP Pin Configuration  
210393–3  
Figure 2. PLCC Pin Configuration  
November 1994  
Order Number: 210393-008  

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