Datasheet > P620-21DC

P620-21DC

更新时间： 2024-02-25 11:02:03

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
7页	212K
描述
Low Phase Noise XO (for HF Fund. and 3-rd O.T.)

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数据手册

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P620-21DC 数据手册

Preliminary PLL620-21

Low Phase Noise XO (for HF Fund. and 3^rdO.T.)

FEATURES

DIE CONFIGURATION

65 mil

•

100MHz to 200MHz Fundamental Mode Crystal.

Output range: 100 – 200MHz (no multiplication).

Selectable OE logic.

Minimum bondwires required for VDD and GND.

Available outputs: PECL or LVDS.

Supports 3.3V-Power Supply.

Available in die form.

(1550,1475)

24 23

GNDBUF

DNC

XIN

Die ID:

A1919-19C

LVDSB

P ECLB

XOUT

DNC

Thickness 10 mil.

VDDBUF

DESCRIPTIONS

DNC

P ECL

PLL620-21 is an XO IC specifically designed to work

with high frequency fundamental and third overtone

crystals. Its design was optimized to tolerate higher

limits of interelectrodes capacitance and bonding

capacitance to improve yield. It achieves very low

current into the crystal resulting in better overall

stability. It offers a selectable OE logic and is ideal

for XO applications requiring LVDS or PECL output

levels at high frequencies.

OE_CT RL

DNC

C502A

LVDS

OUT SEL^

(0,0)

DIE SPECIFICATIONS

BLOCK DIAGRAM

Name

Value

Size

Reverse side

62 x 65 mil

GND

Pad dimensions

Thickness

80 micron x 80 micron

10 mil

X+

X-

Osc illa to r

Amp lifier

OUTPUT SELECTION AND ENABLE

Pad #9

OUTSEL

Selected Output

LVDS

PECL (default)

P LL620-21

Pad #25

OESEL

Pad #30

OE_CTRL

State

Tri-state

Output enabled (default)

Tri-state

(default)

Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”

Pad #30: Logical states defined by PECL levels if OUTSEL (pad #9) is “1”

Logical states defined by CMOS levels if OUTSEL is “0”

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 07/15/05 Page 1

12 3 4 5 6 7

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