Datasheet > P600-37SC

P600-37SC

更新时间： 2024-02-11 06:14:37

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
5页	182K
描述
Ultra Low Current XO 10 MHz to 52 MHz

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中文翻译

获取价格

数据手册

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P600-37SC 数据手册

Preliminary PLL600-27/-37

Ultra Low Current XO 10 MHz to 52 MHz

FEATURES

PIN ASSIGNMENT (PACKAGE)

8 pin SOIC

•

Low phase noise (-130 dBc @ 10kHz offset).

CMOS output with OE tri-state control.

Selectable oscillator “on” or “off” ( Sleep Mode )

feature in output disable mode

Ultra Low current consumption ( <2mA, <1.5mA

at 27MHz, 3.3V respectively for PLL600-27 and

PLL600-37)

XIN/FIN

N/C

XOUT

OE^

GND

VDD

CLK

•

OSCSEL^

^ : denotes internal pull-up

•

Ultra Low disable mode current (<2uA when

disabled with osc. off)

•

10 to 52MHz fundamental or 3^rdOT crystal input.

12mA drive capability at TTL output.

Low jitter (RMS): 2.5ps period jitter.

1.8V, 2.5V and 3.3V DC operation.

Available in 8 pin SOIC, 6 pin SOT or DIE.

6 pin SOT

CLK

GND

VDD

OE^

DESCRIPTION

The PLL600-27/-37 form a low cost family of XO

IC’s, designed to consume the lowest current on the

market for the 10MHz to 52MHz range. It accepts

fundamental resonant mode crystal input from 10 to

52MHz. Providing less than -130dBc at 10kHz offset

at 30MHz and with a very low jitter (2.5 ps RMS pe-

riod jitter) makes this chip ideal for applications re-

quiring low current frequency sources.

XIN/FIN

XOUT

^: denotes internal Pull-up

BLOCK DIAGRAM

SELECTION TABLE

OE^

OSCSEL^*

OUTPUT

Disabled - osc. off

Disabled - osc. on

Enabled

XIN/FIN

XOUT

XTAL

OSC

CLK

OSCSEL

Enabled

^ Internal Pull-up, default value is ‘1’ when not connected.

* Not available in 6 pin SOT package.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 1

12 3 4 5

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